Recessed and Epitaxially Regrown SiGe(B) Source/Drain Junctions with Ni salicide contacts
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Recessed and Epitaxially Regrown SiGe(B) Source/Drain Junctions with Ni salicide contacts Christian Isheden*, Per-Erik Hellström, Henry H. Radamson and Mikael Östling KTH (Royal Institute of Technology), Department of Microelectronics and Information Technology, P.O. Box Electrum 229, SE-164 40 Kista, Sweden. *[email protected] ABSTRACT Integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. When integrated in the PMOS process flow, the resulting Si1-xGex layer is very rough. Several possible causes for low quality epitaxy are discussed and improvements are proposed. It is suggested that the dopant type and/or concentration in the silicon substrate can have an effect on the process. INTRODUCTION As PMOS devices are scaled down, the source/drain extension (SDE) junction depth has to be reduced in order to suppress the short-channel effect (SCE). However, extremely shallow junctions require a resistivity corresponding to doping levels exceeding the B solid-solubility level in Si, which is a fundamental limit for all doping methods based on ion implantation followed by thermal activation. A method to circumvent these problems was proposed some time ago [1]. The method is based on achieving a junction recess using selective, isotropic Si etching, where an in situ B-doped Si1-xGex layer is subsequently grown. Because of the strain compensation effect [2], the doping level in this layer can exceed the solid-solubility level in Si. P-type Si1-xGex is also suitable for Ni salicide formation because it gives rise to a lower Schottky barrier height than p-type Si [3], and the high B incorporation can further lower the contact resistivity. Despite the great potential of this approach, remarkably few studies based on the proposed method have been published. A difficult integration issue is how to preserve the gate oxide between the Si etching step and the epitaxial growth. This issue can be tackled by performing both process steps in a reduced pressure chemical vapor deposition (RPCVD) reactor, using HCl for the recess formation [4, 5]. This work describes several integration issues related to growth of high quality B-doped Si1-xGex layers in a PMOS fabrication process. DEVICE FABRICATION The P doping level in the n-well was 1-2×1017 cm-3 and the physical gate oxide thickness was 29 Å. The fabrication sequence after formation of the gate stack is illustrated in Fig. 1. The p+ poly-Si gate was dry etched using tetraethyloxysilane (TEOS) oxide as a mask for gate definition (a). After gate patterning, another TEOS oxide of 52 nm thickness was deposited and dry etched using reactive-ion etching (RIE) to form sidewall spacers (b). Before being loaded into an ASM Epsilon 2000 RPCVD reactor, the wafers were chemically cleaned using the
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