Recessed Gate Processing for GaN/AlGaN-HEMTs
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Recessed Gate Processing for GaN/AlGaN-HEMTs, Wilfried Pletschen, Rudolf Kiefer, Brian Raynor, Stefan Mueller, Foud Benkhelifa, Ruediger Quay, Michael Mikulla, Michael Schlechtweg, and Guenter Weimann Fraunhofer Institute of Applied Solid State Physics, Freiburg, D-79108, Germany ABSTRACT A dry etch process based on Cl2/SF6 has been developed to selectively remove GaN over AlGaN for the fabrication of recessed gate GaN/AlGaN HEMTs. Using this etching process recessed and nonrecessed FETs were fabricated side by side on the same wafer to provide a fair comparision of data. Recessed gate FETs with a gatelength of 0.15µm show cutoff frequencies of 83 and more than 200 GHz for fT and fmax, respectively. Furthermore, gate-drain breakdown as high as 84V has been obtained which is more than twice as much compared to their non-recessed counterparts. INTRODUCTION Group III-nitride semiconductors are well suited for high power electronic devices due to their unique properties like high electron saturation velocity, high breakdown field and high thermal stability. Due to the polarization induced charges in GaN/AlGaN heterostructures a 2DEG channel is set up without additional doping of the active layers [1]. As has been demonstrated by different authors GaN/AlGaN HEMTs find applications in high-power amplifiers for radar systems operating in the 8 to 12 GHz range and for base stations operating at 3 to 5 GHz [2-4]. However, the properties of the AlGaN surface limit the power performance somewhat. One way to overcome these problems is the use of a GaN cap layer on top of the AlGaN barrier which on the other hand will affect breakdown voltage. To preserve high breajkdown voltage recessing of the GaN cap down to the AlGaN barrier in the gate regime is required. In this work we will describe a low bias dry etch process based on Cl2/SF6 which has been developed to fabricate recessed gate transistors. Furthermore, we will present DC as well as RF data of recessed gate transistors fabricated on a number of wafers and compare them with non-recessed transistors. EXPERIMENTAL Etch process development For the selective removal of GaN over AlGaN Cl2/SF6 based dry etch processes using an ECR etcher have been investigated to study etch rate, selectivity and damage potential. Since the GaN layers to be etched in device fabrication have thicknesses of 5 to 10nm etch rates must be properly adjusted. In order to minimize damage, which is usually related to higher bias potentials, etch rates and bias potential were evaluated over a wide range of rf powers. In a first step GaN and AlGaN samples were etched in parallel using pure chlorine at RF powers ranging from 20 to 85 watts while ECR power was kept constant at 300W. As shown in fig. 1, GaN etch rate as well as bias potential increase almost linearily with rf power in the range 23 to 84 watts. In addition, both materials are etched equally well. For the lowest rf power the bias potential is below 40V at an etch rate of 20nm/min. Since the depth uniformity across a 3 inch wafer is
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