Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing
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Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing Tsuyoshi Setokubo, Eiichi Nakano, Kazuo Aizawa, Hidekazu Miyoshi, Jiro Yamamoto, Takashi Fukada1 and Woo Sik Yoo1 Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198 Japan 1 WaferMasters, Inc. 246 East Gish Road, San Jose, CA 95112 U.S.A. ABSTRACT In every wafer processing step wafer stress management is extremely important for advanced device manufacturing. Thermally induced stress on device wafers has a large impact on lithography and affects device yield. Thermally induced stress during rapid thermal annealing (RTA) steps in high density 512MB DRAM device fabrication was investigated using a lamp-based (cold wall) RTA system and compared to results using a furnace-based (hot wall) single wafer RTA system. Compared to the lamp-based (cold wall) system, RTA in a furnace-based (hot wall) system was found to be very effective in suppressing thermally induced stress and increasing device yield due to superior pattern transfer characteristics in lithography. INTRODUCTION Minimizing the variation in device performance (within wafer and wafer-to-wafer) is very important for device yield management and quality control. For advanced ultra large scale integrated circuit (ULSI) devices, with design rules below 130 nm, the precise control of thermal budget is one of the key issues in thermal processing to optimize device performance. With the shrinkage in device dimensions and allowable thermal budgets, lamp-based single wafer rapid thermal annealing (RTA) systems became very popular addressing thermal processing applications. However, thermally induced stress in wafers during RTA processes can cause small distortions to the wafer surface, which increases the difficulty of subsequent lithography steps. In a lamp-based RTA system (cold wall system) with multiple zone temperature control, the temperature of an individual zone is dynamically controlled using feedback signals from in-situ pyrometric temperature measurements of the zones on the wafer. Precise wafer temperature control and measurement are a technical challenge, as lamp power is constantly modulated by the feedback signals from the wafer temperature monitoring zones. In the dynamic wafer temperature control mode used in the lampbased RTA systems, it is difficult to maintain temperature uniformity during the process. Local and global temperature repeatability depends on many factors, such as the emissivity distribution of the wafer, chamber wall temperature and chamber wall reflectivity. Frequent calibration and maintenance are required. It is well known that RTA processes using conventional lamp-based RTA system generate localized hot and cold spots due to the difference in absorption and emission characteristics within wafers, especially on patterned wafers [1, 2]. Thermally induced stress during RTA processes causes local and global distortions to the wafer surface. As a result, control of the subsequent lithography s
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