Stttdy of Dielectric Caps for Incoherent Lamp Annealing of InP
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STUDY OF DIELECTRIC CAPS FOR INCOHERENT LAMP ANNEALING OF InP
W.J. SODA, J.P. LORENZO, D.F. DAVIFS, AND T.X. RYAN Rome Air Development Center, Hanscom AFB, MA 01731
ABSTRACT A parametric study is presented of CVD and RF sputter deposited SiO2 and PSG dielectric caps for incoherent lamp annealing of InP. Both deposition and annealing parameters are studied. We observe that CVD caps provide reliable mechanical protection during lamp annealing up to maximum 0 bulk temperatures of 930 C, while sputtered deposited Si0 2 caps perform well ,ip to 850nC. We find however that sputter deposited caps introduce process related conduction into both unimplanted and implanted semi-insulating InP. Electrical activation of implanted dopants is also studied as a function of capping technioue. Lamp annealing of InP protected by caps with CVD phosphorus doped Si0 2 in contact with the InP surface, results in excellent activation efficiencies in Si+ implanted material. When properly capped and annealed, we observe electrical profiles whose shape more nearly approaches theoretical LSS, than those previouslv reported.
INTRODUTCTION Successful annealing of ion-implantation induced damage in InP is hampered by the material's high phosphorus vapor pressure at annealing temperatures. The use of incoherent lamps to provide short term heating has been demonstrated to be an attractive alternative to furnace annealing. [1,2] This annealing technique however, places an additional requirement on dielectric caps intended to provide surface protection. These caps must not only resist the sheer stress generated by high phosphorus vapor pressure, but must also tolerate the thermal shock induced by sudden heating and cooling. In this work, we examine RF sputter deposited Si0 2 , chemical vapor deposited (CUD) SiO2 and phosphorus doped Si0 2 (PSC) as annealing caps for incoherent lamp heated InP. We begin with a parametric study of these caps emphasizing only their mechanical integrity. Sputter deposited SiO2 is found to attain the highest bulk sample temperatures without mechanical failure. In certain combinations, we find the CVD caps can attain peak temperatures approaching but not equal to sputtered caps. The effect of the capping and annealing process on electrical properties of unimplanted and Si+ implanted material is also studied. Despite superior mechanical properties, sputter coated InP demonstrates capping induced anomalies which mav significantly alter activation processes for implanted dopants. Preliminary results for Si+ implanted semi-insulating InP are presented. EXPERIMENTAL PROCEDURE CVD cap depostion was performed in a glass and aluminum chamber at atmospheric pressure by oxidation of silane. A Tylan gas control system provided highly repeatable control of deposition cycle timing, P doping, and growth sequence. Samples were heated bv a low mass graphite strip which was in intimate contact with a type K thermocouple. Phosphorus content was estimated from the measurements of Toth et al. [31. Typical deposition
Mat. Res. Soc. Symp.
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