Reliability Issues with Mixed-Signal CMOS Technology
- PDF / 1,239,143 Bytes
- 12 Pages / 414.72 x 648 pts Page_size
- 22 Downloads / 211 Views
47 Mat. Res. Soc. Symp. Proc. Vol. 391 0 1995 Materials Research Society
shown in Figure 2. CLM and DIBL tend to dominate the output resistance at low drain bias, while SCBE becomes significant at high drain bias. Modification of channel profiles by introducing additional process steps to integrate optimized MOSFET for analog applications can dramatically improve drain output resistance ro and transconductance gm (2). The analog part of a circuit must be fully compatible with a process tailored for digital requirements, to reduce process complexity.
0.020
0
10
,
CLM
0.015
D,1,
SCBE
8
0
0.010
n-
Poly Gate
"
126:
n-2
0
0 1
2
3
4
5
Drain Voltage (V)
Figures 1. Schematic of the LATID Process.
Fig. 2. Drain current and output resistance of a submicron MOSFET.
To obtain the desired analog performance, CLM, DIBL, and SCBE need to be addressed simultaneously. Drain engineering provides a cost effective approach to improve analog device characteristics while maintaining digital circuit performance. Among various drain structures, Large-Angle-Tilt Implanted Drain (LATID) provides most flexibility in designing junction depth Xj and gate/n- overlap for analog performance optimization (3,4). By increasing tilt angle, the gate/n- overlap can be increased. On the other hand, the junction depth decreases monotonically with increasing 0 which provides improved CLM and DIBL to compensate for the degradation due to the reduction in Leff. The CLM and DIBL have been maintained at the same level with shallow n- profile even though Leff has been substantially decreased with increasing 0. LATID is also effective in suppressing Isub, mainly due to its increased depletion width at gate/n- overlap region. As shown in Figures 3a and 3b, the Isub/Id ratio in LATID devices are reduced significantly. As a result, voltage gain in LATID devices are improved as compared to LDD devices. Such a reduction in Isub/Id ratio not only improves voltage gain and hot-carrier reliability, but also serves to minimize the crosstalk induced by impact ionization between neighboring analog and digital circuits (5), which is of great importance in high-precision mixed-signal circuits.
48
60
W/L = 36/2.88 urn
W/L = 36/0.65 urn I I ., I
I
1,
,
500
10.08
0.04
SLDD 50 (:C 0
40
-
LATID
0.00
400
0
0.04
8 300 C2
0.02
"0200
30 t 20 F
.
0.03
0
1-
0.02
o.01 0 100
0
10
0
0
1
2
3
4
5
1
Drain Voltage (V)
2
3
4
5
Drain Voltage (V)
Fig. 3a. Voltage gain and the ratio of Fig. 3b. Voltage gain and the ratio of substrate current to drain current substrate current to drain current versus drain voltage for different drain versus drain voltage for different drain structure (Drawn dimension W/L = 36 structure (Drawn dimension W/L = 36 j.tm / 0.65 gm, bias condition: (Id.L)/W== jtm / 2.88 jtm, bias condition: (Id.L)/W = 40 gA and Vgs - Vth - 1.0 V). 40 pA and Vgs - Vth - 1.0 V). Another major issue imposed on submicron analog devices is the hotcarrier-induced degradation, since analog circuits are extremely sensiti
Data Loading...
