Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling
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Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling Andreas Kerber GLOBALFOUNDRIES Inc., 400 Stone Break Road extension, Malta, NY 12020, USA ABSTRACT MG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing. In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies. INTRODUCTION The search of a replacement for conventional SiO2 and SiON gate dielectrics in scaled CMOS technologies started several years [1, 2] before the introduction of metal gate / high-k (MG/HK) in the 45nm CMOS technology node [3]. The industry has successfully qualified replacement metal gate (RMG) [4] and gate first (GF) [5] process technologies and ramped them to high volume manufacturing. The most recent technology nodes have shifted from planar to FinFET device architecture [6]. Despite all those changes, many fundamental aspects related to gate stack reliability remain unchanged including scaling trends for future technology nodes. Time dependent dielectric breakdown (TDDB) shows strong polarity dependence, which can be attributed to the asymmetry in the gate stack. Positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) are seen in RMG and GF integration schemes. The magnitude of the instability, however, is dependent on the device architecture [7, 8]. Moving from bulk planar CMOS devices to bulk FinFET devices, self-heating, which was previously only discussed in partially depleted silicon-on-insulator devices (PDSOI) or fully depleted silicon-on-insulator devices (FDSOI) has become noticeable for bulk FinFET devices. The selfheating effects can lead to enhanced degradation or enhanced recovery adding complexity to the reliability characterization. Another fundamental aspect of reliability in scaled devices is the stochastic nature of the degradation which needs to be comprehended, in particular, for SRAM circuit design. The ongoing search for alternative channel materials to enhance performance of future CMOS technologies will have to meet or exceed the st
