Scaling computation with silicon photonics
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ng computation at constant cost, energy, and footprint The deployment of new information technology must meet both performance and scalability specifications. Information hardware must conform to a common platform to leverage a common research, development, and manufacturing base. System architecture scaling has migrated from central processor units (CPUs) with ever-faster clock frequencies to increasing numbers of processors working in parallel with reduced clock frequencies. This fundamental architectural change resulted from the approach of power density limits as transistor switching voltages reached their scaling asymptote near 0.5 V. Parallel architectures scale linearly in power density with processor count, while continuation of clock frequency scaling at constant voltage would scale as the second or even third power of frequency (P = ½ CV 2f; P = power, C = capacitance, V = voltage, and f = frequency). Multiple processors working in parallel place an emphasis on fast and efficient interprocessor communication. Parallel, communication-centric architectures should ideally possess all-to-all connectivity with zero latency and energy. Software for massively parallel systems must adapt to minimal data movement or to detailed specification of data location and transport in the lines of code. Two vectors of convergence are active in creating scalable
solutions for the next two decades: (1) electronic-photonic convergence to natively integrate communication into the computation process and (2) hardware-software-architecture convergence to provide intelligent, dynamic provisioning of energy-consuming computational resources. Microphotonic integration on the silicon platform embraces both vectors by utilizing the tools of silicon microelectronics and by supporting optimized complexity with novel electronic-photonic partitioning of functionality.1 This article presents the authors’ vision of the grand challenges for new materials, process integration, and foundry manufacturing platforms for scaling computation functionality.
Scaling computation architecture: A connectivity case study The physics of information processing and transport dictates an ultimate tradeoff between clock/communication frequency and parallelism.2 While aggregate bandwidth must continue to scale at all levels of the interconnection hierarchy, the data rates of each channel must reach an asymptotic limit defined by the dissipated power density. Monolithic waveguide integration of optoelectronic devices with transport media, and high index contrast materials, which tightly confine light in dimensions of wavelength/refractive-index and allow for
Lionel C. Kimerling, MIT Microphotonics Center, Massachusetts Institute of Technology, USA; [email protected] Dim-Lee Kwong, Institute of Microelectronics, Agency for Science, Technology and Research, Singapore; [email protected] Kazumi Wada, Department of Materials Engineering; University of Tokyo, Japan; [email protected] DOI: 10.1557/mrs.2014.165
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