Scaling, Power Consumption, and Mobility Enhancement Techniques
The power dissipation of a CMOS circuit consists of the dynamic (due to switching) and the static contribution in the off-state and can be written as (68 ) $$P ={ \sum\nolimits }_{i}{\alpha }_{i}{C}_{i}{V }_{{\it { DD}}}^{2}f + {I}_{ {\it { OFF}}}{V }_{{\
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Scaling, Power Consumption, and Mobility Enhancement Techniques
2.1 Power Scaling The power dissipation of a CMOS circuit consists of the dynamic (due to switching) and the static contribution in the off-state and can be written as [68] P D
X
2 ˛i Ci VDD f C IOFF VDD ;
(2.1)
i
where 0 < ˛i < 1 is the “switching activity factor” of the i th circuit block, Ci is the total effective capacitance including that of all the interconnects and input capacitance of transistors, f is the clock frequency, and IOFF is the total current in the off-state of all the transistorsP biased by the power supply voltage VDD . In contrast to IOFF , the on-current ION D i .ION /i participates in (2.1) indirectly, via the speed requirement f D p=; (2.2) where D Ci VDD =.ION /i ;
(2.3)
and p 1 is the fraction of the fraction of the clock period 1=f taken by the capacitance recharging constant . The model of the power consumption described by (2.1)–(2.3) is approximate, however it captures the basic balance between the static and dynamic components of power generation. At the beginning of the CMOS era the power consumption was reduced by scaling the transistor dimensions and thus the supply voltage VDD down. However, with approaching 100 nm channel size, the VDD scaling has slowed down. One of the reasons was a gradual increase of the currents in the off-state. This increase was mostly due to parasitic leakages, the most important is due to carrier tunneling through a thinner oxide. Indeed, in order to maintain a proper electrostatic control over the channel the thickness of the gate dielectric separating the gate from the channel must be reduced together with scaling of the gate length, which leads to a sharp increase of tunneling through a thin dielectric. With an increase of the off-current one option to preserve the high ratio ION =IOFF is to increase the supply voltage V. Sverdlov, Strain-Induced Effects in Advanced MOSFETs, Computational c Springer-Verlag/Wien 2011 Microelectronics, DOI 10.1007/978-3-7091-0382-1 2,
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2 Scaling, Power Consumption, and Mobility Enhancement Techniques
VDD . This option is, however, unacceptable, since, according to (2.1), it leads to an increase of the power consumption. The industry has faced the problem of increase of heat generation already at the 90 nm technology node. The engineering solution to continue scaling, increase performance, and keep the heat generation under control was the introduction of strain into the channel [20]. Strain modifies the transport properties of the transistor in the open state, while keeping them practically unchanged in the off-state. If the ION current is increased by applying stress, it leads, according to (2.2), to higher speed and performance. Therefore, if a higher ION is achieved for the same IOFF and VDD , the performance gain is accomplished at nearly no increase of the power generation. Alternatively, the performance similar to an unstrained device is achieved at lower VDD and thus reduced power consumption. Although a new technology of hig
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