High Mobility Channel Materials and Novel Devices for Scaling of Nanoeelectronics beyond the Si Roadmap
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High Mobility Channel Materials and Novel Devices for Scaling of Nanoeelectronics beyond the Si Roadmap Marc Heynsa, Florence Bellengerb, Guy Brammertz, Matty Caymax, Stefan De Gendt, Brice De Jaeger, Annelies Delabie, Geert Enemanb,c, Guido Groesenekenb, Michel Houssad, Daniele Leonelli, Dennis Lin, Koen Martensb, Clement Merckling, Marc Meuris, Jerome Mitardb, Julien Penaude, Geoffrey Pourtois, Marco Scarrozzab, Eddy Simoen, Sven Van Elshocht, William Vandenbergheb, Anne Vandooren, Anne Verhulst and Wei-E Wangf IMEC, Kapeldreef 75, B-3001 Leuven, Belgium a also at Department of Metallurgy and Materials Engineering, K.U. Leuven b also at ESAT-INSYS, K.U. Leuven, calso F.W.O.-Vlaanderen d Department of Physics, K.U. Leuven, eRiber assignee at IMEC f INTEL assignee at IMEC
ABSTRACT The use of high mobility channel materials such as Ge and III/V compounds and some novel device concepts are being explored for future CMOS applications. Various passivation schemes are investigated for the Ge surface, such as GeO2 combined with high-κ deposition or the use of a thin Si layer, and demonstrated in short channel Ge MOS devices. Although much progress is being made on the electrical passivation of the III/V materials, typical defect levels remain high at the III/V – high-κ interface. A good insight into the origin of the defects was obtained from a combination of theoretical modeling and experimental data. The use of these new materials also opens the path towards the introduction of novel device structures such as heterojunction Tunnel FET’s, which can be used to lower the supply voltage and reduce the power consumption. The results illustrate the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap. INTRODUCTION Over the last years many new materials have been introduced in advanced CMOS processes in order to continue the scaling and increase the device performance. The introduction of deposited high-κ gate dielectrics with metal gates as a replacement for the thermally grown SiO2 and poly-Si electrode was a major challenge in this respect. For the next generation technology nodes even bigger hurdles will have to be taken since new device structures and high mobility channel materials such as Ge and III/V compounds will be needed to meet the power and performance specifications in future technology nodes. Therefore, the use of high mobility channel materials such as Ge and III/V compounds is investigated for future CMOS applications. In all cases the key challenge is the electrical passivation of the interface between the high-κ dielectric and the alternative channel materials. Since ultimately the major showstopper on the scaling roadmap is not device speed, but rather power density, the introduction of these advanced materials will have to go together with the introduction of new device concepts, such as heterojunction Tunnel FET’s.
PASSIVATION OF Ge SURFACES Initial studies on Ge suggested that a GeO2-like passivation of t
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