III-V CMOS technologies on Si platform
- PDF / 1,332,276 Bytes
- 13 Pages / 612 x 792 pts (letter) Page_size
- 7 Downloads / 207 Views
III-V CMOS technologies on Si platform M. Takenaka and S. Takagi Department of Electrical Engineering and Information Systems, University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
ABSTRACT The heterogeneous integration of III-V semiconductors with the Si platform is expected to provide high performance CMOS logic for future technology nodes because of high electron mobility and low electron effective mass in III-V semiconductors. However, there are many technology issues to be addressed for integrating III-V MOSFETs on the Si platform as follow; high-quality MOS interface formation, low resistivity source/drain formation, and high-quality III-V film formation on Si substrates. In this paper, we present several possible solutions for the above critical issues of III-V MOSFETs on the Si platform. In addition, we present the III-V CMOS photonics platform on which III-V MOSFETs and III-V photonics can be monolithically integrated for ultra-large scale electric-optic integrated circuits. INTRODUCTION The performance of Si LSIs has been enhanced over 30 years by increasing the number of transistors through Moore’s law. As is well recognized, the scaling rule of the Si transistor has made it possible to enhance the performance of the LSIs. However, the miniaturization of the transistors becomes increasingly difficult due to the physical limitations, and the conventional scaling rule will not be enough to enhance the performance of the LSIs. Therefore, some breakthrough technologies are strongly required for the Si LSI in order to enhance the device performance even in the post-scaling era. In addition to the improvement of gate stacks using metal/high-k gate dielectrics and the channel electrostatics control using FD-SOI/multi-gate structures, new channel materials with high mobility and low effective mass are expected to be one of the promising candidates to overcome the scaling rule limit of the conventional Si LSIs. From this viewpoint, III-V compound semiconductors have attracted strong attentions because of high electron mobility and low effective mass as shown in Table 1. The future evolution scenario of CMOS device/process technologies in International Technology Roadmap for Semiconductor (ITRS) 2010 expects that III-V MOSFETs will be introduced into CMOS LSIs in 2018 [1]. Table 1. Electron mobility and hole mobility of Si, Ge, and III-V semiconductors. Si
Ge
InP
InGaAs
Electron mobility (cm2/Vs)
1600
3900
5400
11200
Hole mobility (cm2/Vs
430
1900
200
300
Bandgap (eV)
1.12
0.66
1.34
0.73
However, there are many technology issues to be addressed for integrating III-V MOSFETs on the Si platform as shown in Fig. 1. One of the technology issues is to form high-quality MOS interface. Recent development of Al2O3 gate dielectric deposited by atomic layer deposition (ALD) allows us to form relatively high-quality MOS interface with Dit of ~ 1012 cm-2 eV-1 [2-4], however the origin of interface traps at the III-V MOS interface has not been yet clarified well and further Dit reduction will be required [5-7]
Data Loading...
