High Performance Piplined A/D Converters in CMOS and BiCMOS Processes
This paper describes the design approach and trade-offs in designing high-speed and high performance pipelined A/D converters in CMOS and BiCMOS processes. Design techniques to improve the linearity, lower the noise and reduce the power consumption will b
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High Performance Piplined A/D Converters in CMOS and BiCMOS Processes Ahmed M.A. Ali
Abstract This paper describes the design approach and trade-offs in designing high-speed and high performance pipelined A/D converters in CMOS and BiCMOS processes. Design techniques to improve the linearity, lower the noise and reduce the power consumption will be discussed. The discussion will be in the context of a 16-bit 250 MS/s ADC fabricated on a 0.18 mm BiCMOS process. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, with an input buffer that consumes 150 mW from a 3 V supply. The measured SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency.
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Introduction
The demand for high-resolution A/D converters (ADCs) with ever increasing sample rates has been unabated. Wireless communication applications have been a major driver of the development of this class of ADCs with excellent linearity and IF/RF sampling capability. In addition, other applications, such as instrumentation, medical imaging and military benefit from having ADCs with higher sample rate and higher performance. An attractive architecture for this class of A/D converters has been the pipeline architecture, especially as speeds and bandwidths continue to increase. Their algorithmic nature, amenability to performance enhancement using digital signal processing and their proven ability to achieve superb linearity (up to 110 dB) ensure their dominance for the near future. A block diagram of the pipelined A/D converter discussed in this paper is shown in Fig. 1.1 [1, 2]. Each stage operates in two phases: in the first phase it samples its
A.M.A. Ali (*) Analog Devices Inc, 7910 Triad Center Drive, Greensboro, NC 27409, USA e-mail: [email protected] A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_1, # Springer Science+Business Media New York 2013
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A.M.A. Ali
SNS Calibration Algorithm
Slow Calibration ADC
Input Signal
1 Input Buffer
S/H+ Stage 1 3-bit 6-pF 3
Stage 2 4-bit 1.5pF
Stage 3 3-bit 0.2pF
Stage 4 3-bit 0.1pF
Stage 5 3-bit 0.1pF
Stage 6 3-bit 0.1pF
4
3
3
3
3
3-bit Flash
3
Digital Error Correction
16
Digital Output
Fig. 1.1 Block diagram of the pipelined ADC
input on the sampling capacitor. In the second phase, it digitizes that input and creates a residue to be sampled by the following stage’s sampling capacitance. Each stage consists of a low resolution sub-ADC (usually a flash ADC) that coarsely digitizes the input, and a multiplying DAC (MDAC) that generates and amplifies the residue using a switched capacitor amplifier. To achieve the desired linearity, the capacitor mismatches of the first two stages need to be calibrated. Since those are supply, temperature and sample rate independent, they can be factory calibrated. This is done by using digital coefficients in the digital correction logic that scale the different sub-ranges
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