Sic Power Diodes Improvement by Fine Surface Polishing
- PDF / 319,463 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 30 Downloads / 185 Views
J5.12.1
SIC POWER DIODES IMPROVEMENT BY FINE SURFACE POLISHING P. Godignon1, R. Perez1,3, D. Tournier1, N. Mestres3, H. Mank2 and D. Turover2 1 Centro Nacional de Microelectrónica, CNM-CSIC, Barcelona, Spain 2 NOVASIC, Le Bourget du Lac, France 3 Instituto de Ciencias de Materiales de Barcelona, ICMAB-CSIC, Barcelona, Spain
ABSTRACT Surface treatment is a key technological parameter in the microelectronics technology and especially for SiC devices since high temperatures must be used for implanted impurities annealing and crystal damage recovery. In this work we take profit of a novel fine polishing process developed by NOVASIC to improve the electrical characteristics of Boron and Aluminium implanted Schottky diodes, which are surface quality highly sensitive devices. The mentioned fine polishing process allows to remove a layer thickness of 100nm to 3000nm on the surface of a processed SiC wafer, reducing the surface roughness to RMS of 1Å. The impact of this process on the electrical properties of the samples shows a general improvement of characteristics reproducibility, reduction of leakage current and improvement of breakdown of Boron implanted diodes.
INTRODUCTION Important improvements of the SiC material quality in term of defect density have made in the last years. In addition, diameter of the wafers has been increases up to 3 inches (commercial) [1] and even 4 inches (experimental) [2]. These improvements have allowed considering the production of large area SiC power devices and sensors, and several commercial devices are already available such as Schottky diodes [3,4]. The yield and the performances of the devices highly depend on the starting material quality, but also to a certain extent on the process technology. For most of the SiC planar power devices, P-type doping is necessary, either for the core of the structure such as emitters, or for the high voltage termination structure such as Guard Rings and Junction Termination Extension (JTE) [5,6]. P-type doping is usually done by Aluminium or Boron implantation, since the diffusion coefficients of these impurities in SiC are very low. In addition, a very high temperature anneal (1600-1700ºC) is needed to electrically activate theses impurities in SiC [7-9]. At these annealing temperatures, and depending on the annealing conditions such as ambient and temperature ramp, the surface of the implanted SiC as well as the non-implanted regions of the wafer degrade basically due to an exodiffusion of Silicon, which results in a Carbon rich and disordered layer at the surface after the thermal treatment. When performing the anneal in Argon ambient at 1700ºC, the typical step bunching is formed at the SiC surface, with RMS values that can reach 10nm or more. In addition, other surface degradations occur during processing such as carbon cluster and oxygen rich layer formation after SiC oxidation, surface damage and contamination after RIE or ICP etches, among others.
J5.12.2
Therefore, surface polishing can be considered as a key technological process ste
Data Loading...
