SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge-Condensation Technique for High-Mobility Channel CMOS
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SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge-Condensation Technique for High-Mobility Channel CMOS Devices Tsutomu Tezuka, Tomohisa Mizuno, Naoharu Sugiyama, Shu Nakaharai, Yoshihiko Moriyama, Koji Usuda, Toshinori Numata, Norio Hirashita, Tatsuro Maeda1, Shin-ichi Takagi1, Yoshiji Miyamura2, Eiji Toyoda3 MIRAI-ASET, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan 1 MIRAI-AIST, Chuuou-dai-4, Higashi 1-1-1, Tsukuba, 305-8562, Japan 2 Komatsu Electronic Metals, 3-25-1, Shinomiya, Hiratsuka, Kanagawa, , Japan 3 Toshiba Ceramics, Nishi-Shinjuku Kimuraya Bldg., 7-5-25, Nishi-Shinjuku, Tokyo, Japan ABSTRACT A new fabrication method of SiGe-on-Insulator (SGOI) and Ge-on-Insulator (GOI) structures are presented as well as the application to high-mobility channel CMOS devices. This method, the Ge-condensation technique, consists of epitaxial growth of a SiGe layer with a low Ge fraction on an SOI substrate and successive oxidation at high temperatures, which can be incorporated in conventional CMOS processes. During the oxidation, Ge atoms are pushed out from the oxide layer and condensed in the remaining SiGe layer. The interface between the Si and SiGe layers is disappeared due to the interdiffusion of Si and Ge atoms. Eventually, an SGOI layer with a higher Ge fraction is formed on the buried oxide layer. The Ge fraction in the SGOI layer can be controlled by the oxidation time because total amount of Ge atoms in the SGOI layer is conserved throughout the oxidation process. We found that the lattice relaxation in the SGOI layer also can be controlled through the initial SiGe thickness. P- and n-type strained SOI MOSFETs, which were fabricated on relaxed SGOI substrates formed by this technique, exhibited mobility enhancement of 50% and 80%, respectively. CMOS ring oscillators comprised of the MOSFETs exhibited reduction in propagation delay of 70%-30% compared to a conventional SOI-CMOS device. Ultrathin-body strained SGOI pMOSFETs with high Ge fraction and surface channels were also fabricated by this technique. These devices exhibited hole-mobility enhancement factors up to 2.3. Furthermore, Ge-on-Insulator (GOI) structures with thicknesses less than 10 nm were realized for ultrathin body GOI-CMOS applications by using the Ge-condensation technique. In conclusion, the Ge-condensation technique is a promising technique for fabricating various types of high-mobility channel-on-insulator devices.
INTRODUCTION Combination of a high-mobility channel and a Si-on-Insulator (SOI) MOSFET is expected to overcome issues related to performance degradation of MOSFETs in future technology nodes. A strained Si-on-Insulator (SSOI)-MOSFET is one of the promising devices for high-speed and low power consumption CMOS applications because of the mobility enhancement in both the electron- and hole-inversion layers and low parasitic junction capacitances [1]. Since the strained Si channel layer is epitaxially grown on a strain-relaxed SiGe-on-Insulator (SGOI) substrate, formation of the SGOI substrat
