Sigma-Delta Modulation Based Single-bit Adaptive DSP Algorithms for Efficient Mobile Communication
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Sigma-Delta Modulation Based Single-bit Adaptive DSP Algorithms for Efficient Mobile Communication Aneela Pathan1,2
· Tayab Din Memon3,4
Received: 18 June 2019 / Revised: 12 September 2020 / Accepted: 15 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In the recent past, a new set of digital signal processing algorithms are developed called short word length (SWL) DSP systems to mitigate the multiplier complexity that is an inherent part in most DSP functions. In SWL algorithms, the critical element is sigma-delta modulation (SDM). In this paper, we present the design, implementation, and hardware synthesis of the FIR filter and adaptive algorithms with the conventional and proposed multiplier schemes. Two proposed short word length adaptive algorithms namely Wiener and Steepest-Descent are compared with their counterpart LMS algorithm using conventional and proposed multiplier schemes. The hardware synthesize of these algorithms is done using Xilinx Spartan-6 and Vertex-7 FPGA and comparison is done based on area-performance-power. The overall results show that the sigma-delta modulation based adaptive DSP algorithm outperforms and is an efficient approach for mobile communication. Keywords Sigma-delta modulation · Single-bit adaptive channel equalizer · Wiener · Steepest-Descent · Short word length
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Aneela Pathan [email protected] Tayab Din Memon [email protected]
1
Department of Electronic Engineering, Quaid-e-Awam University of Engineering Science and Technology, QUEST, Larkana, Sindh, Pakistan
2
Institute of Information and Communication Technologies, Mehran University of Engineering and Technology, Jamshoro, Pakistan
3
School of Information Technology and Engineering, Melbourne Institute of Technology, Melbourne, Australia
4
Department of Electronic Engineering, Mehran University of Engineering and Technology, Jamshoro, Pakistan
Circuits, Systems, and Signal Processing
1 Introduction One of the common challenges in the field of communication and those requiring fast computations, like Electronic Products [6], Household Appliances [37], Medical Equipment [32], Automobiles [33], Industrial Applications [20], Aerospace [10], and Social Physics [12], is “data process and analysis” [4, 9, 28, 38]. High-performance DSP systems may achieve these requirements at the cost of more hardware resources consumed due to the intrinsic multiplier complexity [22]. Two ways to reduce the multiplier bottleneck are (a) proposing new multiplier algorithms and (b) reducing the word length of the digital numbers (i.e., short word length). The main element in the short word length DSP system is sigma-delta modulation that was initially introduced to replace PCM in ADCs. Recently, it is reported to be used for developing new DSP algorithms. In [2, 3], authors have reported that with a suitable de-coding circuit at their output ports, FIR digital filters with binary or ternary coefficients could be built. In [36], the authors have followed this ap
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