Silicon Carbide: The Premier Paradigm for Structural and Microelectronic Device Applications in Severe Environments
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particular, the theoretical considerations of Bhatnagar and Baliga [1] indicate the SiC metal-oxide semiconductor field effect transistors would operate within higher voltage and temperature ranges, have superior switching characteristics but with die sizes almost 20 times smaller than similarly rated Si devices. The principal advance which continues to provide a pathway to the realization of superior devices is the aforementioned growth of 6H, and more recently, 4H boules. Systems which employ sublimation of a hotter SiC source material and subsequent condensation of this vapor on a cooler SiC substrate of the desired polytype have been developed [2-4] to achieve reproducible single crystal boules and resultant wafers of acceptable size and electrical quality. The majority of SiC device technology development has taken place since the commercial inception of this process in 1989. The wafer diameter has increased to 1.375 in; further scaling to 3 in. is projected for the end of 1997. The substantially higher carrier mobility of 4H-SiC and the mobility anisotropy that degrades conduction parallel to [0001] in 6H, will likely make the former the polytype of choice, especially for vertical power devices. Wafer resistivities of 0.0028 ohmocm have been reported in 4H [5].
All commercial and essentially all experimental deposition of SiC thin films is achieved via chemical vapor deposition (CVD). Homoepitaxy on vicinal substrates is accomplished via stepflow [6, 7] whereby epilayer growth occurs from the large number of surface steps. Thus the stacking sequence of the Si/C bilayers in the substrate is repeated in the film. Sufficiently high growth temperatures are necessary to achieve an atomic diffusion distance wherein chemisorbed atoms reach the steps before they form nuclei on the terraces; this results in the growth of a 3C film [6], the bilayer stacking sequence on which is mismatched with the 6H or the 4H substrate and results in stacking mismatch boundaries at most of the surface steps. The achievement of n- and p-type doping using nitrogen and aluminum sources, respectively, is routinely accomplished during growth [8] and via high temperature ion implantation [9]. The application of site-competition epitaxy by Larkin et al. [10, 11] whereby C-rich or Si-rich environments are used to block the adsorption of the N or Al species from the surface lattice sites and therefore from doping the film has resulted in the first 2 kV SiC rectifiers ever reported [12]. In like manner, Kordina et al. [13] have used a C-rich environment of a graphite hot-wall reactor to exclude N from p-type layers and to achieve a 4.5 kV SiC diode. Finally, considerable advances have also been made in surface cleaning, dry etching, ohmic and Schottky contacts and insulator growth. A substantial portion of this and the growth and doping research has been reviewed by Davis et al. [14]. The reader should also consult the Proceedings of recent SiC conferences (see e.g., [15]) for additional information. All of these advances have been incorporated
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