Silicon Single Electron Transistors with Single and Multi Dot Characteristics
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Silicon Single Electron Transistors with Single and Multi Dot Characteristics Alexander Savin, Antti Manninen, Jari Kauranen, Jukka Pekola, Mika Prunnila1, Jouni Ahopelto1, Martin Kamp2, Monika Emmerling2 and Alfred Forchel2 Department of Physics, University of Jyväskylä, P.O. Box 35, FIN-40351, Finland 1 VTT Microelectronics Centre, P.O.Box 1101, FIN-02044 VTT, Finland 2 Technische Physik, Universität Würzburg, Am Hubland, D-97074 Würzburg, Germany ABSTRACT Silicon single electron transistors (SET) with side gate have been fabricated on a heavily doped silicon-on-insulator (SOI) substrate. Samples demonstrate two types of characteristics: some of them demonstrate multiple dot behavior and one demonstrates single dot behavior in a wide temperature range. SETs demonstrate oscillations of drain-source current and changes in the width of the Coulomb blockade region with change of gate voltage at least up to 100 K. At temperature below 20 K long-term oscillations (relaxation) of source-drain current after switching the gate voltage has been observed in both multiple dot and single dot samples. Illumination affects both the characteristics of the SETs and the relaxation process. Telegraph noise has been observed in a definite range of source-drain and gate voltages. INTRODUCTION Single electron tunneling devices have attracted considerable attention during the previous decade [1] in a view of perspective of their application as base elements for future nanoscale electronic circuits. One of the limitations of the progress in this direction is the requirement for the size of the structural elements of the devices for room temperature operation, which is below the resolution of modern nanolithography process. Due to the possibility to utilize standard Si technology and use oxidation process for the reduction of the final size of the structures, silicon seems to be a very promising material for nanotechnology. Significant success has been achieved in the development of silicon based SETs operating at rather high temperature [2-5], as well as logic elements [6,7] and memory modules [8,9] based on single electron effect. Usually the Si based SETs demonstrate complicated multiple dot behavior at low temperature [2-5,10-12], but in some ranges of gate voltage [12] or at higher temperature, when the smallest dot determines the properties of the SET [4,11], they can demonstrate single dot behavior. High level of doping and implantation procedure introduce additional defects, that may lead to enhanced telegraph noise caused by random trapping and emitting of the electrons by trapping centers in the tunnel barrier or near to the dot [ 13,14] and to slow processes due to relaxation of background charge at low temperature [14,15]. In this paper we report on results of investigation of side-gated silicon single electron transistors fabricated on a heavily doped thin SOI substrate. Some of these results will be published elsewhere [16]. SAMPLES Silicon SETs with side gate have been fabricated on a heavily doped SOI wafer. The SOI film h
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