C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structur
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C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure Shaoyun Huang, Souri Banerjee, and Shunri Oda Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, JAPAN ABSTRACT We prepared a SiO2/nanocrystalline Si (nc-Si)/SiO2 sandwich structure. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-Si dots has been observed at room temperature. The peak in conductance around flat band condition indicates that a trap event had occurred where an electron is stored per nc-Si dot. A logarithmic charge loss function is found and this discharging process is independent of the thermal activation mechanism. The longer memory retention time and logarithmic charge loss in the dots are explained by a “built-in” electric field through the tunnel oxide, which varies with time, resulting in a variable tunneling probability. The electric repulsion induced by the built-in electric field hinders the discharging of electrons remained in the dots. INTRODUCTION Metal-Oxide-Semiconductor field-effect-transistor (MOSFET) memory structures based on silicon-quantum-dots or nanocrystals have recently attracted great interest both for new physical phenomena and for potential applications in next generation memory devices [1,2], in which silicon nanocrystals, embedded in the oxide layer between the control gate and channel, act as floating memory nodes. Many works have been devoted to fabricate ideal memory structures and to obtain reproducible hysteresis in current-voltage (I-V) characteristics [3,4]. However, the retention mechanism corresponding to interface defects are still unclear. In this kind of devices, the defects associated with nanocrystalline silicon (nc-Si) often results in the long-term memory retention time [5]. In our previous work, Hinds et. al. investigated the retention time distribution in MOSFET memory devices and found the interface states were not the dominant mechanism for electron storage in the investigated device structure [6]. However, the detail retention mechanism (dots charging and discharging processes) should be further understood, which will directly give large influence on fast write/erase and long-term charge retention time in the device. The capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are useful and sensitive tools for investigating interface characters between Si and SiO2. Kohno et. al. investigated the transient current of a Si quantum dot floating gate MOS structure with tunnel gate oxide and showed a charging and discharging process in C-V characteristics with short retention time [7]. In our work, we fabricate a SiO2/nc-Si/SiO2 sandwich structure. These structures rather differ from those obtained using Si+ implantation or Si-rich film followed by annealing, where a wide distribution in space and size of dots would result in a large lateral current leakage and degrade the device performance [8,9]. The charging and dischargin
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