SONOS memory devices with ion beam modified nitride layers

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SONOS memory devices with ion beam modified nitride layers D. Simatos1, P. Dimitrakis1, V. Ioannou-Sougleridis1, P. Normand1, K. Giannakopoulos1, B. Pecassou2 and G. BenAssayag2 1 2

Institute of Microelectronics, NCSR “Demokritos” Attika, Greece. CEMES-CNRS, Toulouse, France.

ABSTRACT In this work we examine the development of ion beam modified oxide-nitride-oxide structures formed by low-energy (1 keV) implantation of Si, N and Ar ions (1x1016 ions/cm2) into oxide-nitride gate stacks and subsequent wet-oxidation to form the blocking oxide. Transmission electron microscopy indicates that the thickness of the blocking oxide layer is strongly affected by the implantation process going from 1 nm (non-implanted sample) to 4-5 nm (N and Ar implants) and 7.5 nm (Si implant). The Si implanted stacks exhibit the highest attainable memory window (~ 8.5 V for a 1 ms pulse regime), which involve both electron and hole storage. In contrast the thinner blocking oxide that develops to the nitrogen and argon implanted stacks limits the memory window which is due only to electron trapping. Room temperature charge retention measurements of the programming state reveal that the electron loss rate is faster in samples implanted with Si than N, allowing for a memory window of 1.7 V and 2.5 V respectively after ten years extrapolation. This retention behavior is mainly attributed to the different nature of the traps generated in the implanted materials. INTRODUCTION The SONOS (silicon-oxide-nitride-oxide-silicon) type memory devices constitute a promising scaling alternative to the conventional floating-gate cells, especially for embedded applications [1]. However, this class of non-volatile memory cells, which typically make use of oxide-nitride-oxide (ONO) charge-trapping (CT) stacks, requires improvements mainly in regards of the erase operation [2]. The most important approach for the improvement of the CT memories is the replacement of one or more layers of the dielectric stack by high-permittivity dielectric materials which aims to enhance the erase operation and the charge retention properties [3-5]. In parallel to the above main stream approaches we recently demonstrated a new method to synthesize CT memories of improved performance which utilizes low-energy Si implantation into an oxide-nitride stack followed by low-thermal budget wet oxidation [6]. In this work we extend further this method by studying the dependence of the control oxide formation during wet-oxidation upon the implanted species. For this purpose a comparison is performed between silicon which is highly reactive to water and much less reactive elements like nitrogen and argon. In addition to structural studies, the electrical and the memory properties of the resulting structures are reported. EXPERIMENTAL

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Typical oxide-nitride stacks (2.5 nm/ 6 nm) were formed on n-type silicon substrates. The stacks were implanted with 1 keV Si, N and Ar ions to a dose of 1016 ions/cm2, and further wet oxidized at 850 oC for 15 min. The structural characteristics of th

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