STI Pattern Density Characterization for the System on a Chip

  • PDF / 2,288,632 Bytes
  • 9 Pages / 417.6 x 639 pts Page_size
  • 93 Downloads / 171 Views

DOWNLOAD

REPORT


have been evaluated and their respective processes optimized through the Design of Experiments (DOE). Figures 1 and 2 show the trench erosion measured on the STI monitor for both slurries corresponding to CMP DOE process conditions. Characterization of pattern density dependency are conducted on 4 mask sets with different device blocks and pattern densities: Mask A: mixing blocks of high- and low-density devices; Mask B: mixing patterns of MIT test structure; Mask C: low density blocks only; Mask D: low density blocks filled with dummy structure. Factors evaluated in this program include slurry selectivity, polish time, trench etch, film deposition, and dummy structure. Finally, physical and electrical data are correlated to determine if the process window is robust enough for volume production.

RESULTS AND DISCUSSION Effect of Slurry Selectivity Mask A has 4 device blocks of various densities (two of them are identical), as shown in Figure 3. Calculations based on a CAD tool indicates the local chrome densities of the layout ranging from 50% in 500gm x 500ý±m cells. Wafers prepared with the mask were polished to certain trench oxide thickness by high-selectivity slurry (HSS) and by low selectivity slurry (LSS) separately. Comparison for device wafers is made based on the difference of the remaining nitride thickness, as shown in Figure 4. On the large feature (STI monitor) and high density structure (test chip), the nitride remaining with HSS is larger than that with LSS; however, on the low density features (memory and logic blocks), the nitride loss with HSS is more significant than that with LSS corresponding to most test conditions of over-polish (10-/o-40%). Since the low density features are of our most interest, the subsequent discussion will focus on LSS. Polish Time Dependency Mask B (MIT test structure) offers a wide range of pattern densities from 0% to 100% by different combination of feature sizes and pitch distances in 2mm x 2mm cells. Wafers prepared with Mask B were polished for 120s, 135s and 150s. The remaining oxide and/or nitride thickness is shown in Figure 5. At 120s, the polish process reaches the nitride layer on the features with pattern densities