Strain scaling for CMOS
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history of strain engineering in planar CMOS technology Over the past few decades, a great deal of theoretical and experimental work has been carried out in the field of carrier transport in strained semiconductors;1 however, it was not until the late 1990s that strained channels were viewed as requisite elements in complementary metal–oxide–semiconductor (CMOS) technology. Since then, a variety of innovative techniques have been devised and integrated as strain-inducing elements into existing CMOS technology. For example, compressive and tensile stressed silicon nitride liners,2 wafer-scale biaxial strain,3 local epitaxial stressors for uniaxial strain,4 and even the strain fields surrounding defects5 have been used to improve the current drive of modern field-effect transistors (FETs). Here, we explore the most successful of these strain-inducing approaches in planar FET technology, namely lattice-engineering by epitaxial growth. We begin by presenting some of the early work on biaxial strain engineering for FET applications that showed a promising path for drive current enhancement by improving the electron and hole mobility in Si. We then describe the introduction of process-induced uniaxial strain and its advantages compared to biaxial strain with respect to drive current in scaled FETs. Finally, the limitations of strain scaling and possible future strategies are explored.
The perfect miscibility of the Gex Si(1–x) alloy system permits control of the lattice parameter from that of Si (0.543 nm) to that of Ge (0.566 nm) by controlling the composition during epitaxial growth. Because the lattice parameters of these alloys are larger than that of Si, subsequent layers of Si grown on relaxed Gex Si(1–x) alloy layers will be under tensile strain. Early work6 on thick, strain-relaxed compositionally graded Gex Si(1–x) layers grown on Si substrates demonstrated that although relaxation was dislocationmediated, defect densities could be made relatively low (∼106 cm–2). Shortly thereafter, some of the first strained-Si FET devices were fabricated using thin Si layers grown on these thick, relaxed Gex Si(1–x) graded buffer layers (GBLs) formed on Si substrates. The amount of (biaxial) tensile strain in the thin Si channel layer was varied by controlling the Ge content in the GBL. This process of engineering the lattice parameter directly on the starting substrate prior to device fabrication would eventually be referred to as “wafer-scale” or “global” strain. The main advantages to this approach were that the magnitude and uniformity of the strain could be well-controlled, and standard device fabrication steps could then be used. Both electron3 and hole7 mobilities were shown to improve significantly with increasing strain in long-channel FETs fabricated on biaxially strained Si using this approach.
S.W. Bedell, IBM T.J. Watson Research Center; [email protected] A. Khakifirooz, IBM T.J. Watson Research Center; [email protected] D.K. Sadana, IBM T.J. Watson Research Center; [email protected] DOI: 10.1557/mrs.2014.5
© 2014 M
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