Stress-Induced Voiding vs Temperature and Passivation Thickness: IN Al-0.5%Cu-2%Si, Al-0.5%Cu and Al-1%Si
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STRESS-INDUCED VOIDING VS TEMPERATURE AND PASSIVATION THICKNESS IN AI-0.5%Cu-2%Si, AI-0.5%Cu AND AI-1%Si T. D. SULLIVAN AND L. A. MILLER IBM Technology Products, Essex Junction, VT 05452
ABSTRACT Stress-induced voiding in microelectronics chips has been reported to exhibit a variety of dependencies on temperature and on passivation stress. The dependence of line failure is reported here at four different temperatures (150, 225, 285, and 315 'C) for AI-0.5%Cu-2%Si, AI-0.5%Cu and AI-1%Si lines with passivation thicknesses (silicon oxide or silicon nitride) ranging from 0.1 to 2.5 times the metal thickness. Failure distributions change in a complex manner with changing passivation thickness, and with temperature for a specific passivation thickness, raising questions on the validity of using the conventional median time to failure (t,,) and lognormal slope (a) to project field failure rates from data generated by accelerated life testing.
INTRODUCTION Stress-induced void formation, also known as thermal voiding or creep voiding, in microelectronic circuit chips has been a recognized reliability detractor since 1984 when it was first reported by Curry et al.1 Since then, considerable work has been done to understand and counter its effects so that so-called 'high-technology' metallizations (those in high density, multilevel interconnect schemes) are well protected against failure by thermally induced voiding. Alloying elements have been added to the Al to make it more stress resistant (e.g., Cu, Pd), passivation deposition temperatures and properties have been altered to reduce the stress experienced by the Al, and redundant layers, typically of refractory metals (e.g., Ti, W), have been added above and below the Al alloy layer to provide alternate conductive paths around voids. With all of these protective measures, why continue to study the behavior of stressinduced voiding? There are at least three reasons. First, new chip technologies are continually being designed and introduced into manufacturing, and these new technologies must be qualified. Qualification means, among other things, that the reliability of the new technology has been evaluated and determined to be within specified customer requirements. This cannot be fully determined if stress-induced void formation is not sufficiently understood. An example of a situation where knowledge of voiding kinetics is required is shown in Fig. 1., which shows a cross section of two levels of metallization connected by a W stud. Both levels of wiring have redundant metal layers both above and below the Al layer. However, it is possible during formation of the W stud to overetch the via hole to the extent that the top redundant layer of the lower wiring level is completely perforated, leaving only the perimeter of the stud in contact with it. Should the fabrication process accidentally break this perimeter contact, an open circuit in the wiring is possible by formation of a stressinduced void directly under the stud, as shown. Without proper understanding of voiding ki
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