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EFFECT OF SILICON THICKNESS AND SURFACE PASSIVATION ON THE CHARACTERISTICS OF AMORPHOUS SILICON THIN FILM TRANSISTORS G.E. POSSIN and F.C. SU GE Corporate Research and Development, P.O. Box 8, Schenectady, NY 12301

ABSTRACT Passivation of the back channel of thin film a-Si:H FETs is discussed. A onedimensional model is used to predict the effect of back surface interface state density on the threshold voltage and subthreshold slope. A passivation method is described which results in a very high density of interface states. Two methods based on dual gate FETs are used to determine the interface state density. The principal effect of this method of passivation is to make the threshold voltage and subthreshold slope dependent on silicon thickness. This dependence is verified experimentally. For silicon > 150 nm, the dependence is weak. Variations in the deposition temperature of the passivation dielectric and the use of SiNX and SiO. are shown to have only a small effect. INTRODUCTION One of the most common types of a-Si TFT is the inverted staggered structure. In common with all thin film field effect transistors, it shares the problem of passivation of the back interface, i.e., the interface not nearest the control gate (VG1). It is generally believed that the passivation of the back interface should be as perfect as possible. That is, have a minimum density of interface states and fixed interface charge. The passivation method described here results in a very high density of interface states (>2 x 103a#/cm 2 /eV). We

will describe a model calculation which predicts the behavior of TFI's as a function of the interface state density and other parameters, and compare in some cases to experimental results. The advantages and disadvantages of this method of passivation are discussed. One additional result of this investigation is the demonstration of two methods for measuring very high density of interface states using very small area FETs. DEVICE FABRICATION Devices were fabricated using PECVD n'-a-Si (50 nm), n'-a-Si (200 nm), and a-SiNs (150 nm) deposited in a single chamber at 13.56 MHz, a power density of 0.5 W/cm2 , pressure of 400 to 900 mT, and 300 °C. Contacts are sputtered Mo and the gate metal is sputtered Ti. After the Mo S-D metal is etched, the n' is removed from the channel using a timed etch in a barrel plasma etcher with CF 4 + 02. Typically, 80 nm of Si is removed. After etch, the surface is cleaned in organic solvents, rinsed in DI water, and baked in air at 250 'C for at least 30 min. The passivation is then completed with a PECVD film of a-SiNs or a-SiO_ at temperatures between 150 and 300 TC. For many of the studies in this report, a second control gate (VG2) of patterned sputtered Mo is added on top of the 100 nm passivation layer, resulting in a dual gate structure similar to that described in [1].

Mat. Res. Soc. Symp. Proc. Vol. 118. '1988 Materials Research Society

256

RESULTS We have used a model [2] similar to that described by Powell and Pritchard [3]. Our method of solution is disting