Structural and Chemical Characterization of Tungsten Gate Stack for 1 Gb Dram
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STRUCTURAL AND CHEMICAL CHARACTERIZATION OF TUNGSTEN GATE STACK FOR 1 Gb DRAM O. Gluschenkov1, J. Benedict1, L.A. Clevenger1, P. DeHaven1, C. Dziobkowski1, J. Faltermeier1, C. Lin2, I. McStay2, K. Wong1 1
IBM Microelectronics, Semiconductor R&D Center, Hopewell Junction, NY; Infineon Technologies, Hopewell Junction, NY; DRAM Development Alliance IBM/Infineon, IBM Semiconductor Research & Development Center, Hopewell Junction, NY. 2
Abstract Material interaction during integration of tungsten gate stack for 1 Gb DRAM was investigated by Transition Electron Microscopy (TEM), X-ray Diffraction analysis (XRD) and Auger Electron Spectroscopy (AES). During selective side-wall oxidation tungsten gate conductor undergoes a structural transformation. The transformation results in the reduction of tungsten crystal lattice spacing, re-crystallization of tungsten and/or growth of grains. During a highly selective oxidation process, a relatively small but noticeable amount of oxygen was incorporated into the tungsten layer. The incorporation of oxygen is attributed to the formation of a stable WOx (x800°C) the sacrificial barrier decomposes and reacts with Si to form a thermally stable diffusion barrier SiWxNy.5,8 Upon word line patterning the gate stack needs a side-wall oxidation to repair the gate oxide damaged at the corners. The side-wall oxidation process is referred to as a selective side-wall oxidation process since it oxidizes Si selectively leaving the tungsten layer intact.6-8 Although an acceptable performance of W-gate-stack transistor was demonstrated, interaction of materials during gate stack processing is not fully understood. This report is devoted to materials aspects of the W gate stack integration.
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Experimental The metal gate stack was fabricated on standard 8-inch (200mm) Si wafers. A standard trench-DRAM-compatible process flow was used up to the gate dielectric deposition. A thin SiO2 layer was used as a gate dielectric. An in situ doped poly Si layer was deposited onto the SiO2 layer by a CVD technique. Before metal/barrier deposition, the native oxide formed on the surface of poly Si was stripped in HF solution. WNx sacrificial barrier was deposited by a PVD method using an Ar/N2 ambient. Deposition of pure W was achieved by changing the PVD tool ambient to Ar gas only. The W layer was capped with a SiN film. After deposition, the gate stack was patterned and etched. Selective side-wall oxidation process was conducted in an Applied Materials Centura RTP system.7,8 TEM cross section of the integrated W-stack is shown in Fig. 1. Blanket monitor wafers were processed along with the patterned wafers for the analysis of stack materials modification and interaction during the processing. Processed blanket films were analyzed with X-ray diffraction (XRD), Auger electron spectroscopy, and resistivity measurement. X-ray diffraction scans were run using monochromatic Fe radiation from a sealed tube source operating at 35kV and 35mA. Scans were run from 30 to 140° 2θ, with a step size of 0.1° and count
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