Dielectric breakdown Characteristics of poly-Si/HfAlOx/SiON gate stack
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Dielectric breakdown Characteristics of poly-Si/HfAlOx/SiON gate stack Kazuyoshi Torii, Hiroshi Ohji, Akiyoshi Mutoh, Takaaki Kawahara, Riichiro Mitsuhashi, Atsushi Horiuchi, S. Miyazaki1 and Hiroshi Kitajima Semiconductor Leading Edge Technologies, Inc. (Selete) 34, Miyukigaoka, Tsukuba-shi, Ibaraki-ken, 305-8501, Japan 1 Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8560,Japan ABSTRACT The dielectric breakdown behavior of poly-Si gate CMOSFETs with HfAlOx/SiON gate dielectric fabricated using mass production worthy 300 mm process was investigated. If SiO2 is used as an interfacial layer (IL), the IL reduction and the intermixing between the HfAlOx layer and the IL occurred, which causes extrinsic breakdown. By using the SiON of [N]=18% as an IL and setting the maximum temperature after the HfAlOx deposition to be 1000°C, the interfacial reaction was suppressed and the extrinsic breakdown component was eliminated. In the case of the n-capacitor accumulation, an abrupt increase of gate leakage was observed, which is believed to correspond to the IL breakdown. The mean time to failure (MTTF for 0.1cm2 at 125ºC) is long enough. On the other hand, gate current initially decreases and then starts to increase in the case of p-capacitor accumulation. If we define the time to breakdown at the onset of current increase, the MTTF would be only 3.7 years if it obeys the V-plot (MTTF predicted by 1/V-plot was 1.6x107 years). INTRODUCTION The aggressive reduction of the gate insulator thickness in complementary metal oxide semiconductor (CMOS) devices leads to excessive gate leakage currents, especially in low power devices. Therefore, alternative gate insulators with high dielectric constant (high-k) have been intensively studied. The integration of the high-k gate insulator into sub-100 nm FET has already been demonstrated; however, there are a few reports on their reliability. Moreover, most of the reliability researches were using a gate insulator whose EOT was relatively thick, and/or using a metal gate electrode1,2 though a EOT less than 1.5nm is required and poly-Si gate electrode would be used in the 65nm-node low power devices. This is mainly due to the difficulty in fabricating devices with thin EOT-gate insulator using conventional CMOS processing, in which high temperature process is done after the gate stack formation. We use hafnium aluminate (HfAlOx), which is a mixture of HfO2 and Al2O3, as a candidate of gate insulator material for poly-Si gate CMOS devices. Although it is amorphous up to 1000°C if the Hf concentration (Hf/(Hf+Al)) is less than 30%, the interfacial reaction between HfAlOx and Si substrate3 prevents uniform device fabrication. In this study, we investigated the interfacial reaction dependence on the process temperature and on the nitrogen concentration in the interfacial layer between HfAlOx and Si substrate. Based on these investigations, we succeeded in fabricating a poly-Si/HfAlOx/SiON gate stack whose EOT was 1.5nm with good uniformity. The dielectric break
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