Structure and Characteristics of Strained-Si-On-Insulator (Strained-SOI) MOSFETs
- PDF / 1,147,363 Bytes
- 13 Pages / 612 x 792 pts (letter) Page_size
- 89 Downloads / 167 Views
Structure and Characteristics of Strained-Si-On-Insulator (Strained-SOI) MOSFETs Shin-ichi Takagi, Tsutomu Tezuka, Naoharu Sugiyama, Tomohisa Mizuno and Atsushi Kurobe Advanced LSI Technology Laboratory, Corporate Research & Development Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210-8582, Japan ABSTRCT Strained-Si MOSFET is an attractive device structure to be able to relax several fundamental limitations of CMOS scaling, because of high electron and hole mobility and compatibility with Si CMOS standard processing. In this paper, we present a new device structure including strained-Si channel, strained-SOI MOSFET, applicable to CMOS under sub-100 nm technology nodes. The main feature of this device is that thin strained-Si channel/relaxed SiGe heterostructures are formed on buried oxides. The principle and the advantages are described in detail. The strained-SOI MOSFETs, whose electron and hole mobility is 1.6 and 1.3 times, respectively, higher than in conventional MOSFETs, have successfully been fabricated by combining the SIMOX technology with re-growth of strained Si films. We also present novel fabrication techniques to realize ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with high Ge content, including Ge condensation due to oxidation of SGOI with lower Ge content. Strained-Si/SGOI structures with total thickness of 21 nm and Ge content of 56 % have been fabricated by oxidizing SiGe films on conventional SOI substrates and re-growing strained-Si films. INTRODUCTION A driving force of CMOS scaling is to obtain higher current drive and lower supply voltage simultaneously, in addition to the increase in packing density of devices. However, further reduction of channel length and oxide thickness becomes more difficult for sub-100 nm MOSFETs and beyond, because of several fundamental limitations including direct tunneling gate current and inversion-layer capacitance. Thus, attention is currently being paid to MOSFETs with high mobility channels, which are expected to provide higher carrier velocity through velocity overshoot effect [1-3]. As a result, channels with high carrier mobility enable to reduce Vdd with keeping constant current drive. On the other hand, another indispensable factor in the application of new materials to scaled CMOS is the compatibility with Si LSI processes. From these viewpoints, strained Si is becoming one of the most promising materials for MOSFET channels, because of larger electron and hole mobility and the compatibility with Si LSI technology [4-14]. Furthermore, we have recently proposed a new device structure using this strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFETs, where a strained-Si film is formed on a buried insulating layer [15-18]. This paper describes the basic concept, device structures and electrical characteristics of this strained-SOI MOSFET. After summarizing the electronic properties of strained-Si films and MOSFETs, the concept and the advantages of strained-SOI MOSFETs are described. Next, the fabrication
Data Loading...
