Sub-Threshold Performance Assessment of Ultra-Thin Body InGaAs-on Insulator Negative Capacitance MOS Transistor
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ORIGINAL PAPER
Sub-Threshold Performance Assessment of Ultra-Thin Body InGaAs-on Insulator Negative Capacitance MOS Transistor Subir Kumar Maity1 Received: 22 May 2019 / Accepted: 17 December 2019 © Springer Nature B.V. 2020
Abstract In this work, with the help of 2-D device simulation and 1-D Landau-Khalatnikov model for ferroelectric material, we have studied the scaling effect of ferroelectric material as a gate dielectric on the sub-threshold characteristics of ultra-thin body on insulator MOS transistor. The device performance is investigated for the MOS device with high mobility III-V material (InGaAs) as a channel material and its performance is compared with silicon channel based MOS device. The negative capacitance characteristics of the dielectric material is modeled by charge-dependent 1-D L-K equation related to ferroelectric polarization model. With an increase in thickness of ferroelectric material, improvement in sub-threshold characteristics such as drain induced barrier lowering coefficient and sub-threshold swing is observed. At higher ferroelectric layer thickness, hysteresis effect in the device characteristics also observed. Internal gate voltage amplification found to be proportional with the thickness of ferroelectric region for both device. With optimum ferroelectric layer thickness, device with high mobility InGaAs channel shows significant improvement in electrostatic integrity which is comparable to silicon channel based MOS device. Keywords Ferroelectric · Negative capacitance · Polarization · Sub-threshold swing
1 Introduction Due to continuous down-scaling of MOS transistors, source and drain junctions becomes much more abrupt. As a result, parasitic capacitance associated with source/drain junction also increases. Enhanced short channel effects due to poor electrostatic integrity in scaled transistor cause degradation in sub-threshold swing (SS). For the logic application, one transistor must change its state from OFF to ON condition as fast as possible. This is difficult to achieve in deeply scaled transistors due to degraded sub-threshold characteristics. Also, degradation in ON current and ION /IOF F factor put some limitation in the scaling of supply voltages [1]. High mobility III-V channel materials such as InGaAs are attractive choice among researchers due to their excellent transport property governed by low electron effective mass, high electron mobility and high saturation Subir Kumar Maity
[email protected] 1
School of Electronics Engineering, Kalinga Institute of Industrial Technology (KIIT), Bhubaneswar, Odisha, Pin-751024, India
velocity. For same amount of sheet charge density, higher value of drain current can be achieved using III-V semiconductor as channel material compared to Silicon based MOS device. However, one of the major drawbacks related to III-V MOSFETs are poor electrostatic integrity. Due to higher permittivity of III-V semiconductors, electrostatic coupling between source and drain is expected to be higher which enhances short channel effects
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