Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics
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Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics Nihar R. Mohapatra, Madhav P. Desai, 1Siva G. Narendra, V. Ramgopal Rao Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India 1 Microprocessor Research Lab, Intel Corporation Hillsboro, OR, USA Abstract The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations. Introduction With the aggressive reduction of MOS transistor dimensions into the deep sub-micrometer regime, alternate high dielectric constant (Kgate) insulators are becoming indispensable in order to avoid the unacceptable high direct tunneling current of the conventional silicon dioxide [1]. Some of the high-K materials such as Al2O3 (K~10), HfO2/ZrO2 (K~25), La2O3 (K~27), TiO2 (K~60-100) have been widely studied[2-3]. The main idea is to achieve an equivalent oxide thickness of less than 15Å by combining higher K with greater physical thickness to prevent direct tunneling. Unfortunately higher physical gate dielectric thickness (by a factor of Kgate/KSiO2) results in higher fringing fields from gate to source/drain regions thereby weakening the gate control [4-6]. The reduction of channel length further increases the ratio of physical gate dielectric thickness to channel length. Thus two-dimensional effects become dominant leading to poor short channel performance. In this paper, we have studied the effect of channel length, junction depth and overlap length scaling on the performance of deep sub-micron MOS transistors with high-K gate dielectrics. The effect of dielectric stack and spacer dielectric on the transistor performance is also presented. For this purpose, extensive simulation data is generated using two-dimensional device simulator MEDICI [7]. Results are presented in this work, which give a better insight into the physics of MOS transistors with high-K gate dielectrics. Simulation Structures Device simulations are performed using a two-dimensional (2-D) device simulator MEDICI [7]. The simulated structures are based on the scaled dimensions outlined in the SIA roadmap. A B3.3.1 Downloaded from https://www.cambridge.org/core. University of Arizona, on 27 Jul 2018 at 06
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