Surix: Non-blocking and low insertion loss micro-ring resonator-based optical router for photonic network on chip
- PDF / 1,544,926 Bytes
- 23 Pages / 439.37 x 666.142 pts Page_size
- 41 Downloads / 149 Views
Surix: Non‑blocking and low insertion loss micro‑ring resonator‑based optical router for photonic network on chip Sanaz Asadinia1 · Mahdi Mehrabi1 · Elham Yaghoubi2 Accepted: 28 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Photonic network-on-chip is utilized as a candidate paradigm for important attributes such as high bandwidth and low energy consumption. In this paper, a non-blocking five-port photonic router is proposed for the 2-D mesh topology, which is called Surix. Surix has been designed for improving the physical layer and the network’s performance parameters in multi-core network topologies. Moreover, a new routing algorithm on Surix is proposed, in which turning models and the circuit switching method are used for mitigating photonic insertion loss and power consumption of the photonic layer. The proposed algorithm can select various source and destination nodes through the selected routes with the lowest insertion loss and power consumption. The simulation results show that Surix outperforms conventional routers in network performance parameters. For instance, the insertion loss of Surix in the mesh topology shows a 9.92–37.15 percent improvement compared to conventional routers. Keywords Micro-ring resonator · Non-blocking · Optical routers · Optical interconnects · Optical loss · Optical network on chip · Turn model algorithms
* Mahdi Mehrabi [email protected] Sanaz Asadinia [email protected] Elham Yaghoubi [email protected] 1
Department of Computer Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran
2
Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran
13
Vol.:(0123456789)
S. Asadinia et al.
1 Introduction With the emergence of complex computer applications including cloud computing and artificial intelligence, using multi-core processors has become one of the best solutions for improving the performance of complex computations. The network-on-chip (NOC) paradigm effectively utilizes several processors for parallel computing. To increase the speed of NOC, which uses electronic connections, we can increase the clock frequency power, which will lead to an increase in the performance. However, on the other hand, this will increase power consumption as well. To overcome this challenge, using photonic NOC (PNOC) instead of NOC with electronic connection has been proposed, which provides higher connection bandwidth, lower transmission delay, and lower energy costs [1]. PNOC is based on the photonic technology and utilizes photonic connections based on silicon and devices that are compatible with the CMOS technology [2–4]. Its performance can be significantly increased using the wavelength-division multiplexing (WDM) since photonics can obtain higher bandwidth density compared to electronics using the WDM. In the recent years, various designs have been proposed for photonic network-on-chip, and many of these designs show a significant improvement compared to their elec
Data Loading...
