Temperature and Frequency Dependencies of Charging and Discharging Properties in Mos Memory Based on Nanocrystalline Sil
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TEMPERATURE AND FREQUENCY DEPENDENCIES OF CHARGING AND DISCHARGING PROPERTIES IN MOS MEMORY BASED ON NANOCRYSTALLINE SILICON DOT Shaoyun Huang, Souri Banerjee, and Shunri Oda Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552, JAPAN ABSTRACT Temperature and frequency dependencies of the electrical properties of SiO2/nanocrystalline Si (nc-Si)/SiO2 sandwich structures have been studied. A clear positive shift in capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics suggests electron trapping in nc-Si dots. The role of interface states and deep traps in these devices has also been examined, which shows that they have little effect on the overall device performance. INTRODUCTION In our previous report [1], it was pointed out that electron charging and discharging processes in metal-oxide-semiconductor field-effect transistor (MOSFET) memory structures based on silicon quantum dots can be accurately detected by capacitance-voltage (C-V) and conductance-voltage (G-V) techniques. In this work, we will focus on the temperature and frequency dependencies of C-V and G-V measurements, which reveal the role of defects in the structure. Although much work has been devoted to fabricate ideal memory structures and to obtain reproducible hysteresis in the current-voltage (I-V) characteristics [2,3], the retention mechanism associated with interface defects is still not clear. Kohno et al. investigated the transient current of a Si quantum dot floating gate MOS structure and showed a charging and discharging process. However, effects of interface defects were not apparent in their study [4]. On the other hand, Shi et al. claimed that deep level defects would often result in long-term retention behavior [5], whereas, Hinds et al. concluded that interface defects did not play a dominant role in charge retention mechanism in MOSFET memory devices [6]. Hence further study on the retention mechanism in relation to interface defects would be helpful as it generally has a large influence on overall device performance. EXPERIMENTAL DETAILS The memory device investigated in the present report is a SiO2/nanocrystalline Si (nc-Si) dot/ SiO2 sandwich diode structure on an n-type silicon substrate. For comparison, control samples having similar structure but without nc-Si dots were also prepared. The detailed fabrication processes of such a device have been described elsewhere [1]. The electrical properties of this sandwich structure device were measured by HP4156B precision semiconductor parameter analyser and HP 4284A precision LCR meter in the temperature range between 30 K and room temperature.
A12.5.1 Downloaded from https://www.cambridge.org/core. Access paid by the UCSF Library, on 24 Oct 2019 at 22:14:57, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/PROC-715-A12.5
RESULTS A typical memory device sample consists of nc-Si dots (1.4x1011/cm2) with 8 nm diameter, sandwiched be
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