Temperature Dependent Performance Evaluation and Linearity Analysis of Double Gate-all-around (DGAA) MOSFET: an Advance
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ORIGINAL PAPER
Temperature Dependent Performance Evaluation and Linearity Analysis of Double Gate-all-around (DGAA) MOSFET: an Advance Multigate Structure Yogesh Pratap 1
&
Jay Hind Kumar Verma 2
Received: 10 October 2019 / Accepted: 12 December 2019 # Springer Nature B.V. 2020
Abstract Multi-gate devices such as double gate, FinFET and Gate-All-Around (GAA) are potential candidates to achieve the performance expected by semiconductor association. This paper presents an analog/RF performance and linearity distortion analysis for an advance multigate structure named Double Gate-All-Around (DGAA) MOSFET. Temperature dependent characteristics of the DGAA MOSFET have also been investigated in detail from 200 K to 400 K. A comparative analysis between Gate-All-Around (GAA) and DGAA MOSFETs with impact of silicon film thickness is analyzed by using 3-D ATLAS TCAD device simulator. It is demonstrated that depending on gate voltage, DGAA MOSFET has larger value of drain current (Ids), transconductance (gm) and gain. Results demonstrate that drain current, transconductance, device gain and transconductance to drain current ratio (gm/ Ids) improves when temperature is decreased. DGAA MOSFET shows improvement in analog/RF performance, suppressed Short Channel Effects (SCEs) and harmonics distortions due to more gate controllability on the channel charge. Keywords Double gate-all-around (DGAA) MOSFET . Inner and outer gate . Harmonic distortion . Linearity1
1 Introduction The improved performance and higher packing density of semiconductor devices in Integrated Circuits (ICs) continuously motivate the device scientists to reduce the feature size of single transistor into nanoscale regime. According to ITRS, the technology node will reach atomic level (below 5 nm) by 2020 [1, 2]. This can be achieved by reducing the short channel effects (SCEs) with scaling the device for more controllability over the channel. For this, the multiple gate structures such as double gate (DG) [3, 4], Fin-FET [5] and Gate-AllAround (GAA) [6, 7] are becoming cornerstone for sub-32 nm
* Yogesh Pratap [email protected] Jay Hind Kumar Verma [email protected] 1
Department of Instrumentation, Shaheed Rajguru College of Applied Sciences for Women, University of Delhi, New Delhi 110096, India
2
Department of Electrical Engineering Indian Institute of Technology, Kanpur, UP, India
technologies having enhanced channel charge controllability by the gate. Although these multiple gate structures exhibit better short channel immunity but their performance degrades with the decrease in gate length. Therefore it is the need of hour to refine the device fundamental techniques for the survival of nano-electron device technology. For gate-all-around nanowire FETs, the charge is centroid and the maximum leakage point in the sub-threshold regime is the center of the nanowire [8]. In the sub-threshold regime, if charge can move towards centroid and the maximum leakage point to the outer channel region and thus, get closer to the gate, it may lea
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