Tetrahedral Amorphous Carbon Thin Film Transistors
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Mat. Res. Soc. Symp. Proc. Vol. 423 0 1996 Materials Research Society
the extreme left of the picture and five distinct layers can be identified by Fresnel contrast. The lighter regions marked A, C and E correspond to regions of lower density which, using nanometre spatial resolution techniques, have been shown to be sp2 rich [7]. The graphitic layer at the top surface is of the order of 1 - 2 nm and 3 - 5 nm at the bottom interface with the substrate. Such layers will lead to the pinning of the Fermi Level and prevent transistor action. The device structure and the fabrication process must therefore allow this layer to be removed.
I/>~.+ B
A
Si
WI D
C
E
5nm
Figure 1. Cross-sectional bright field TEM of a ta-C double layer on silicon [7]. From the several TFT structures available a coplanar type was chosen for the final device. This configuration has several advantages: the graphitic layer on the top surface is thinner and the least contaminated; the top layer can be easily accessed to allow etching off of the sp 2 layer and; the subsequent deposition of the gate insulator layer can be effected in the same pump down sequence thereby minimising the chance of the sp 2 layer reforming and reducing potential contamination problems at this critical interface. Device Fabrication A lift -off process was used to pattern a 50 nm thick layer of undoped ta-C into 1.2 x 0.6 mm islands on a Coming 7059 glass substrate. Aluminium was then deposited by thermal evaporation and patterned to define the source and drain contacts. The graphitic layer on the top surface of the ta-C islands was then etched away in an N20 plasma and a 400 nm layer of PECVD silicon nitride was then immediately deposited to form the TFT gate insulator. An aluminium top gate contact completed the process. A detailed description of the device fabrication is given in [8] and a layout of the completed planar structure is shown in Figure 2.
S-channel
width (W)
Source channel
-\
length (L)
PP
Drain Drain
',.,,
ta-C is andsi (1.2 mm x0.6mm)
Fgr2.Lyu
t
Gate W
1.mm L =C20Tum
c
Figure 2. Layout of the coplanar ta-C TFT Structure
40
A typical transfer characteristic for a device produced using undoped ta-C as the active layer is shown in Figure 3. This device operates in the p-channel mode. As the bias on the gate is ramped from + 100 V to - 100 V the drain current increases by 1 to 2 orders. For all devices tested the gate leakage is less than a few picoamps. 10 0
W = lO0WRm
L = 20tm
0 Ct
0 () 0-
0
1.0
0
0
0
C
0
0
V D= 50V
10
0
l 01
50
100
0.1 -100
-50
0
Gate Voltage (V) Figure 3. Transfer Characteristic for p-channel ta-C TFT
Figure 4 shows a series of drain characteristics for the same device. The drain current is clearly modulated by the applied gate voltage. However, no saturation in the drain characteristics has been observed, even for drain voltages as high as 100 V. The low drain current at low drain bias may be attributed to the poor ohmicity of the aluminium source and drain contacts to ta-C
layer. We are
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