Thin Oxide Defects Resulting from Plasma Induced Wafer Charging
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THIN OXIDE DEFECTS RESULTING FROM PLASMA INDUCED WAFER CHARGING Sychyi Fang, and James P. McVittie Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070
ABSTRACT EEPROM charge monitors reveal that an 02 plasma induces a negative charge which peaks at the wafer center for the asher used. The charge damage to small gate area MOS capacitors is investigated by using "antenna" structure. The post plasma interface state density increases with increasing antenna size and varies by two orders of magnitude. A hole trapping induced breakdown mechanism during plasma charging is supported by new experimental evidence such as the annealing and polarity effects of charge-to-breakdown and tunneling currents. Where stressing has not being severe, these hole traps are annealable at T > 6501C, while in severely stressed areas early breakdown occurs which is not annealable.
1 INTRODUCTION Plasma processes are widely used in VLSI manufacturing to lower process temperature and to obtain directional ion bombardment. By their nature, plasmas always result in some wafer surface charging which is normally not significant. However under some conditions which are not well understood, thin oxides under a gate can be severely degraded by this charging, resulting in a decrease in breakdown voltage [1] [2] [3]. This surface charging may also induce surface states at the Si/SiO 2 interface and trap charge in the oxide even if early breakdown is not produced. Fast ramp voltage measurements have been used in most previous studies to characterize this plasma damage. However, this technique is primarily sensitive to catastrophically damaged oxides and cannot give information on the trapped charge in the oxide which affects long term oxide reliability. Furthermore, most published work in this field has used large gate oxide area test structures where pinholes and weak oxide spots tend to control breakdown. Breakdown occurs in these localized regions first [4], hence obscuring the phenomena associated with the intrinsic breakdown mechanism. In this work, damage to small gate oxide area MOS capacitors is investigated by using large area poly-Si pads to serve as "antennas" to increase the induced field in the thin oxide during plasma processing [5]. A number of damage sensitive electrical measurements have been used to characterize the nature of the plasma damage to the oxide. New experimental evidence is presented to highlight the degradation mechanism during plasma processing. Furthermore, the annealing effects on oxide damage are investigated.
2 EXPERIMENT Polysilicon gate MOS antenna capacitors on 5 ohms-cm < 100> Si wafers were used in
this study. The thin gate oxide was grown in dry 02 at 850'C to a thickness (t,) of 12 nm Mat. Res. Soc. Symp. Proc. Vol. 262. 01992 Materials Research Society
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Quartz Chamber Wafer
Figure 1: Schematic diagram of a single wafer 02 plasma asher. and the field oxide thickness was 1.7 fim. The antenna-to-gate area ratio (Af/Ag) was varied from 16 to 1000 for gate oxide areas (A,) of 20 x
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