Tree-based Heterogeneous FPGA Architectures Application Specific Exp
This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to me
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Umer Farooq Zied Marrakchi Habib Mehrez •
Tree-Based Heterogeneous FPGA Architectures Application Specific Exploration and Optimization
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Umer Farooq COMSATS Institute of Information Technology Kamboh House Syed Chiragh Shah Town Kasur 55050 Pakistan
Habib Mehrez Paris VI Laboratoire LIP6 Université Pierre et Marie Curie 4, Place Jussieu 75252 Paris France
Zied Marrakchi FLEXRAS Technologies Boulevard Anatole Tour Pleyel Ouest 153 93521 Saint Denis France
ISBN 978-1-4614-3593-8 DOI 10.1007/978-1-4614-3594-5
ISBN 978-1-4614-3594-5
(eBook)
Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2012937466 Ó Springer Science+Business Media New York 2012 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
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Preface
The generalized and programmable nature of Field Programmable Gate Arrays (FPGAs) has made them a popular choice for the implementation of digital circuits. However, the programmability of FPGAs makes them larger, slower, and more power consuming than their counterpart ASICs; hence making them unsuitable for applications requiring high density, performance, and low power consumption. The main theme of this work is to improve the area of FPGAs. For this purpose, a detailed exploration and optimiza
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