Voltage-controlled magnetoelectric memory and logic devices

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troduction Static random-access memory (SRAM) technology is widely used today for on-chip registers and cache memory in modern microprocessors because of its fast access times (1015 read/write cycles). However, SRAM density is limited and its static power dissipation and cell size (in terms of F2, where F is the feature size) continue to increase. Thus nearly all high-density working memories (dynamic random-access memory [DRAM]) are off-chip with high energy cost and slow access speeds, the latter of which has been historically known as the memory wall or von Neumann bottleneck (Figure 1a).1 The situation is further exacerbated with the advent of big data and artificial intelligence, which demand fast access to large amounts of data at high processing speeds. One solution is to use high-density nonvolatile memory (NVM) with increased on-chip capacity to minimize access to the distant

off-chip DRAM through the central processing unit (CPU)/ DRAM bus, thus improving the system-level latency and energy performance. As illustrated in Figure 1b, with a much smaller cell size than SRAM, emerging high speed and endurance NVM technologies have the potential to implement nonvolatile on-chip cache with higher density.2 Another more aggressive solution would be to use NVM cells as storage elements with logic functionalities (in memory computing),3 thus eliminating standby power consumption and enabling instantON operation, as shown in Figure 1c. This class of NVM will therefore become a strong candidate to realize novel computing paradigms that are energy efficient, nonvolatile, memory centric, and highly parallel. Magnetic random-access memory (MRAM) that utilizes collective spin phenomena, originating from spin–orbit coupling (SOC), to store information is one of the most promising NVM candidates in this class. To date, almost all

Xiang Li, Materials Science and Engineering Department, Stanford University, Stanford, USA; [email protected] Albert Lee, Electrical and Computer Engineering Department, University of California, Los Angeles, USA; [email protected] Seyed Armin Razavi, Electrical and Computer Engineering Department, University of California, Los Angeles, USA; [email protected] Hao Wu, Electrical and Computer Engineering Department, University of California, Los Angeles, USA; [email protected] Kang L. Wang, Departments of Physics, Electrical and Computer Engineering, and Materials Science and Engineering, University of California, Los Angeles, USA; [email protected] doi:10.1557/mrs.2018.298

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• VOLUME 43 • DECEMBER Cornell 2018 • www.mrs.org/bulletin © 2018 Materials Downloaded MRS fromBULLETIN https://www.cambridge.org/core. University Library, on 01 Sep 2020 at 08:34:53, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/mrs.2018.298

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Voltage-controlled magnetoelectric memory and logic devices

Figure 1.  Computing systems architectures at present and in the future, only including computation chip and main me

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