Zr Oxide Based Gate Dielectrics with Equivalent SiO 2 Thickness of Less than 1.0 nm and Device Integration with Pt Gate
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Zr OXIDE BASED GATE DIELECTRICS WITH EQUIVALENT SiO2 THICKNESS OF LESS THAN 1.0 nm AND DEVICE INTEGRATION WITH Pt GATE ELECTRODE Yanjun Ma and Yoshi Ono Sharp Laboratories of America, 5700 NW Pacific Rim Blvd, Camas, WA 98607 ABSTRACT ZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ~35 fF/µm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application. INTRODUCTION With shrinking device feature sizes, the semiconductor industry is facing serious challenges on many technology fronts. One of the grand challenges is the replacement of the SiO2/poly-Si gate stack with new gate dielectrics and gate electrodes. There are many material choices in the search for a replacement for SiO2, including TiO2, Al2O3 and Ta2O5, and more recently, Zr and Hf oxides and silicates [1-10]. In this work we report on the investigation of zirconium oxide dielectrics which showed promise for use to equivalent oxide thickness (EOT) < 1.0 nm. In particular, we concentrate on the scaling limit of ZrO2. This information will greatly aid in the selection of a SiO2 replacement. A maximum accumulation capacitance about 35 fF/µm2 with a leakage current less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film. This puts the scaling limit of ZrO2 to an EOT of below 0.5 nm. Al doping (~25% by XPS) is used to increase the crystallization temperature of the gate dielectrics. Submicron MOSFETs with these gate dielectrics have been fabricated with a nitride replacement process. Excellent characteristics have been achieved, demonstrating the feasibility of integrating this gate dielectric in a CMOS process flow. Together with new high k gate dielectrics, dual metal gate schemes may be needed within the next few years to enable the continued scaling of CMOS devices. Low work function metals are needed to replace n+ polysilicon for NMOSFETs and high work function metals are needed to replace p+ polysilicon in PMOSFETs. While there are many materials with the right work function for NMOS, including Al, Ta, TaN, Mo, and Zr, there are few materials that have an appropriate work function for the gate electrode of the PMOSFET. Pt has one of the highest work functions for pure metals and is a strong candidate for the gate electrode of PMOS metal gate device. In this work we also demonstrate the feasibility of fabricating Pt damascene gate and integrating it with a ZrO2
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based high κ gate dielectric in PMOS transistors. Our results show that the Pt ga
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