A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces
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A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces Antonio C. Oliver1 and Jack M. Blakely Materials Science & Engineering, Cornell University, Ithaca, NY 14850, U.S.A. ABSTRACT Surface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current. INTRODUCTION Surface morphology is believed to play a role in several aspects of the electrical performance of MOS devices with characteristic dimensions that are very small [2-6]. In previous work, we have shown how silicon surface step morphology influences the Si-SiO2 interface morphology and outer SiO2 surface morphology for oxidized silicon surfaces. Based on the finding that the Si-SiO2 interface step morphology is largely determined by the starting silicon step morphology of the substrate [1,7,8], and considering the variation in oxide thickness caused by atomic steps at the interface [2], it should be possible to measure the effect of surface step morphology on electronic properties metal-oxide-semiconductor stacks. In an ideal capacitor, no current will flow through the plates after it charges. However, in real capacitors there is usually some small amount of charge leakage that results in a measurable current. The cause of this leakage current can be attributed to several factors; in this paper, the effect of interface step morphology on leakage current is studied. Specifically, the leakage current due to electron tunneling is considered by fabricating capacitors with thin SiO2 dielectric layers on areas with greatly reduced step density and also on areas of a sample without reduced step density. Clearly, the Si-SiO2 interface for a capacitor fabricated on a surface area which has had steps removed or the number of steps greatly reduced will be much smoother than a capacitor made on a surface area where steps and step bunches remain. For these experi
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