Ion Implantation Through Thin Silicon Dioxide Layers for Si-based Solid-State Quantum Computer Device Development
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1074-I12-05
Ion Implantation Through Thin Silicon Dioxide Layers for Si-based Solid-State Quantum Computer Device Development Jeffrey C. McCallum1, Michael L. Dunn1, and Eric Gauja2 1 School of Physics, University of Melbourne, Swanston Street, Melbourne, 3010, Australia 2 School of Physics, University of New South Wales, NSW, Sydney, 2052, Australia ABSTRACT Ion implantation doping of Si through an SiO2 overlayer is of interest for fabrication of a range of devices on the pathway to the development of a solid–state quantum computer (SSQC). The fabrication requirements of devices based on the Kane architecture typically involve implantation through a pre-existing thin device–quality thermal oxide at low fluences ~1011 cm-2 and ion energies in the range 10 – 20 keV. Here we present results from deep level transient spectroscopy studies of ion–implanted MOS capacitors in which interface–trap densities have been measured in as–grown and H–passivated thermal oxides and in ion implanted and rapid– thermally processed devices. For thin oxides of 5 nm or less and low ion fluences we find that implantation does not significantly increase interface trap densities and somewhat surprisingly that it can even be beneficial when the interface trap density is abnormally high, ~ 1×1011 cm−2 .eV −1 , in the as-grown oxide. INTRODUCTION Ion implantation doping of Si through an SiO2 overlayer is of interest for fabrication of advanced metal-oxide field effect transistors (MOSFETs) and for a range of devices of interest in the development of a solid–state quantum computer (SSQC). SSQC–related devices that are currently being fabricated by our Centre include electrically detected magnetic resonance devices where spin-dependent transport is measured [1] and devices where charge transfer occurs between quantum dots [2] or between individual or small clusters of donors [3]. The implantation requirements of the devices typically require low fluences ~1 × 1011 cm-2 for the gate region of gated-devices although fluences as high as ~1 × 1014 cm-2 have been used for fabrication of source-drain leads in some cases. Implantation of the gate region typically requires ion energies in the range 10 – 20 keV and implantation through a pre-existing thin device– quality thermal oxide typically ~5 nm in thickness. For SSQC devices based on the Kane architecture [4] in which qubits are envisaged to consist of individual phosphorus atoms that are individually gated, the thermal processing steps that are used to activate the implanted ions and repair the oxide and substrate damage should ideally result in very limited diffusion of the implanted ions. Deep level transient spectroscopy (DLTS) in its various forms provides a convenient means of identifying and quantifying the electrically–active defects introduced within the bulk and at the SiO2–Si interface by the oxide–growth and implantation processes and
it can be used to monitor their removal via subsequent annealing steps. Of particular importance to the SSQC fabrication program is the fact that DLTS
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