A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems
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A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems Camel Tanougast Laboratoire d’Instrumentation Electronique de Nancy, Universit´e de Nancy I, BP 239, 54600 Vandoeuvre L`es Nancy, France Email: [email protected]
Yves Berviller Laboratoire d’Instrumentation Electronique de Nancy, Universit´e de Nancy I, BP 239, 54600 Vandoeuvre L`es Nancy, France Email: [email protected]
Serge Weber Laboratoire d’Instrumentation Electronique de Nancy, Universit´e de Nancy I, BP 239, 54600 Vandoeuvre L`es Nancy, France Email: [email protected]
Philippe Brunet Laboratoire d’Instrumentation Electronique de Nancy, Universit´e de Nancy I, BP 239, 54600 Vandoeuvre L`es Nancy, France Email: [email protected] Received 27 February 2002 and in revised form 12 September 2002 We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigurable processors. In this case, the number of cells in the reconfigurable array is an implementation constraint and the goal of an optimised partitioning is to minimise the processing time and/or the memory bandwidth requirement. Here, we present a strategy for partitioning and optimising designs. The originality of our method is that we use the dynamic reconfiguration in order to minimise the number of cells needed to implement the data path of an application under a time constraint. This approach can be useful for the design of an embedded system. Our approach is illustrated by a reconfigurable implementation of a real-time image processing data path. Keywords and phrases: partitioning, FPGA, implementation, reconfigurable systems on chip.
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INTRODUCTION
The dynamically reconfigurable computing consists in the successive execution of a sequence of algorithms on the same device. The objective is to swap different algorithms on the same hardware structure, by reconfiguring the FPGA array in hardware several times in a constrained time and with a defined partitioning and scheduling [1, 2]. Several architectures have been designed and have validated the dynamically reconfigurable computing concept for the real-time processing [3, 4, 5]. However, the mechanisms of algorithms optimal decomposition (partitioning) for runtime reconfiguration (RTR) is an aspect in which many things remain to do. Indeed, if we analyse the works in this domain, we can see that they are restricted to the application development approach
[6]. We observe that: firstly, these methods do not lead to the minimal spatial resources. Secondly, a judicious temporal partitioning can avoid an oversizing of the resources needed [7]. We discuss here the partitioning problem for the RTR. In the task of implementing an algorithm on reconfigurable hard
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