Memory Design Techniques for Low Energy Embedded Systems
Memory Design Techniques for Low Energy Embedded Systems centers one of the most outstanding problems in chip design for embedded application. It guides the reader through different memory organizations and technologies and it reviews the most successful
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Memory Design Techniques for Low Energy Embedded Systems
by
Alberto Macii Politecnico di Torino, Torino, Italy
LucaBenini Universita di Bologna, Bologna, Italy
and
Massimo Poncino Universita di Verona, Verona, Italy
SPRINGER-SCIENCE+BUSINESS MEDIA, B.Y.
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-4953-0 ISBN 978-1-4757-5808-5 (eBook) DOI 10.1007/978-1-4757-5808-5
Print'ed on acid-free paper
All Rights Reserved © 2002 Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers, Boston in 2002
No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner.
Contents
Preface Acknowledgments
IX Xl
1. INTRODUCTION
1
1
Power Metrics
3
2
Power Dissipation Sources
4
3
System-Level Design and Low-Power Issues
4
Low-Power Embedded Systems
5
Focus and Organization of the Book
5 7 9
2. APPLICATION-SPECIFIC CORE-BASED SYSTEMS
13
ASIC Design Trends
14
The Role of Embedded Memories Process-Compatible Embedded Memories 2.1 2.2 Dedicated-Process Embedded Memories
19 21 23
3
Practical Examples 3.1 Emotion Engine 3.2 MPEG4 Core 3.3 Single-Chip Voice Recorder
26 27 30 33
4
Summary
36
1 2
3. ENERGY OPTIMIZATION OF THE MEMORY SUB-SYSTEM
37
1
Memory Hierarchy
38
2
Energy-Efficient Memory Hierarchy Design 2.1 Explorative Techniques 2.2 Memory Partitioning
40 42 43
v
MEMORY DESIGN TECHNIQUES
VI
2.3
Extending the Memory Hierarchy Bandwidth Optimization Memory Interface Optimization Other Techniques
45 46 48 50
4. APPLICATION-SPECIFIC MEMORIES 1 Energy Requirements of Caches 1.1 Cache Architecture 1.2 Cache Energy Model 2 Application-Specific Memory (ASM) 2.1 Memory Array 2.2 Decoding Logic and Hit Function 2.3 ASM-Based Architectures Case Study 3 4 Experimental Results
51 52 53 55 56 56 58 59 61 65
3 4 5
5. APPLICATION-DRIVEN
MEMORY PARTITIONING 1 Low-Power Memory Partitioning 2 Recursive Memory Partitioning 2.1 Cost Metrics 2.2 Partitioning Algorithm 2.3 Multi-Way Partitioning Algorithm Evaluation 2.4 Physical Design of the Partitioned Memory 3 3.1 Decoder Generation Memory Generation 3.2 3.3 Block Placement 3.4 Routing Power Estimation 3.5 3.6 Delay and Area Estimation 4 Experimental Results Partitioning Overhead Characterization 4.1 4.2 Energy Optimization Sensitivity to Data Values 4.3
6. APPLICATION-SPECIFIC
CODE COMPRESSION Selective Instruction Compression 1
69 70 73 74 75 77
79 81 83 84 85 86 87 88 89 90 92 95 99 99
Contents 2
3 4
5
Vll
Instruction Memory Architectures 2.1 Evaluation Metrics 2.2 Code Compression Schemes Decompression Unit Experimental Results 4.1 Off-Chip Program Memory 4.2 On-Chip Program Memory Memory Usage Control in Code Compression
7. PERSPECTIVES
103 104 105 109 113 113 116 118 125
Index 141
Preface
Memory system design for multi-
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