A Novel Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor Fabricated by using a Selective Si
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0910-A22-11
A Novel Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor Fabricated by Using a Selective Side Etch Process Ta-Chuan Liao1, Chun-Yu Wu2, Feng-Tso Chien3, Chun-Chien Tsai1, Hsiu-Hsin Chen1, Chung-Yuan Kung2, and Huang-Chung Cheng1 1 Institute of Electronics, National Chiao Tung University, No. 1001 Ta Hsueh Rd., Hsinchu, 300, Taiwan 2 Department of Electrical Engineering, National Chung Hsing University, No. 250 Kuo Kuang Rd., Taichung, 402, Taiwan 3 Department of Electronic Engineering, Feng Chia University, No. 100 Wenhwa Rd., Taichung, 407, Taiwan Abstract: A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6×107, and off-state leakage current at VGS = -10 V and VDS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs). I. Introduction Poly-Si thin film transistors (TFTs) have been widely applied as switching elements in active-matrix flat panel electronics such as liquid crystal displays (LCDs), 1 and organic light-emitting diodes (OLEDs). 2 The poly-Si TFTs exhibit higher driving current than the conventional amorphous silicon TFTs. For the further development, highly versatile circuits and systems need to be fully integrated on the display panel substrate, which is the concept of system-on-a panel (SOP).3, 4 Unfortunately, conventional poly-Si TFTs suffer from an anomalous off-state leakage current, which increases with gate voltage and drain voltage. This undesirable off-state leakage current prohibits the use of poly-Si TFTs in many high-performance circuit applications. The dominant off-state leakage current is due to the field emission via grain boundary traps induced by the high electric field in the drain depletion region.5, 6 It has been widely reported that the offset-gated 7, and lightly doped drain (LDD) 8 poly-Si TFTs can effectively reduce the maximum drain electric field in the channel. However, the offset-gated poly-Si TFTs cause a high parasitic resistance in the offset region which severely decreases the on-current. Besides, in LDD structure, the device degradations due
to the additional n- implant damage caused by low-temperature activatio
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