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B10.4.1

Strained Channel Transistor Using Strain Field Induced By Source and Drain Stressors Yee-Chia Yeo, Jisong Sun, and Eng Hong Ong. Silicon Nano Device Lab, Dept. of Electrical & Computer Engineering, National University of Singapore, Singapore 117576. ABSTRACT We perform a theoretical evaluation of the strain field in a p-channel transistor with silicongermanium (Si1-yGey) stressors in the source and drain regions. The strain field comprises a lateral compressive strain component and a vertical tensile strain component. The lateral strain component is larger in magnitude and more uniformly distributed as compared to the vertical strain component. The impact of transistor design parameters, such as the Ge mole fraction y in the stressors, the spacing L between stressors, the stressor depth, and the raised stressor height, on the strain field are investigated. Hole mobility enhancement larger than 30% is achievable wth L = 50 nm and y = 0.15. More aggressive mobility enhancement targets may be achievable by reducing the stressor spacing and employing a stressor with a larger lattice mismatch with the Si channel.

INTRODUCTION Strain engineering in the channel region of metal-oxide-semiconductor field-effect transistors (MOSFETs) is being actively pursued for enhancing carrier mobility and drive current. A stressor, i.e. stress-inducing structure, in the vicinity of the channel is usually employed for channel strain engineering. For example, a relaxed silicon-germanium (SiGe) layer underlying a Si channel region may be used as a bottom stressor to introduce biaxial strain for significantly improved electron and hole mobility [1-2]. A top stressor, such as a high stress silicon nitride film formed over a transistor structure, has also been employed to enhance electron mobility in n-channel transistors [3-4]. Very recently, it was found that source/drain (S/D) regions comprising SiGe generate significant compressive stress in the transistor channel, leading to enhanced hole mobility in p-channel transistors [5-6]. While transistors with SiGe S/D regions have been demonstrated before [7-8], relatively little is known about the strain effects, such as the origin of the strain field, the magnitude and distribution of the strain components, and their relationship to hole mobility enhancement. In this paper, we perform a theoretical evaluation of the strain field in a p-channel transistor with lateral lattice-mismatched SiGe source/drain (S/D) stressors. The dependence of the strain components on transistor design parameters such as inter-stressor spacing, stressor lattice constant, stressor depth, and use of raised/non-raised stressors is investigated. Hole mobility enhancement and potential scalability of the transistor structure are also discussed.

B10.4.2

TRANSISTOR STRUCTURE AND FINITE ELEMENT CALCULATIONS Fig. 1 (a) shows a p-channel transistor with lateral lattice-mismatched stressors (LLS) or SiGe in the S/D regions. The lattice constant of Si1-yGey is given by aSiGe = (1-y)·aSi + y·aGe, where aSi = 5.431 Å