Self-Aligned Nanocrystalline Silicon Thin-Film Transistor With Deposited n + Source/Drain Layer
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0989-A11-02
Self-Aligned Nanocrystalline Silicon Thin-Film Transistor With Deposited n+ Source/Drain Layer I-Chun Cheng1,2, and Sigurd Wagner1 1 Department of Electrical Engineering and PRISM, Princeton University, Princeton, NJ, 08544 2 Graduate Institute of Electro-Optical Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, 10617, Taiwan ABSTRACT We demonstrated self-aligned nanocrystalline silicon (nc-Si:H) n-channel thin film transistors (TFTs) with directly deposited n+ layer. The silicon layers were deposited by plasmaenhanced chemical vapor deposition at a substrate temperature of 150°C. The TFTs were made in a staggered top-gate, bottom-source/drain geometry with a seed layer underneath. The selfalignment of top-gate to the bottom-source/drain was achieved by backside exposure photolithography through the glass substrate and the silicon layers, followed by a lift-off process. An extent of gate to source/drain overlap of 1.5 µm was obtained. The self-aligned TFTs have similar characteristics to their non-self-aligned counterpart. This result represents an important step toward directly deposited nc-Si:H TFT backplanes on plastic substrates. INTRODUCTION Large-area electronics on clear plastic substrates are under intense research and development for their light weight and flexibility. These attributes are desirable for applications in flexible transmissive or bottom-emitting displays. However, commercially available clear plastic substrates limit the fabrication of thin-film electronic circuits to process temperatures of less than ~ 200°C. Therefore, electronic materials compatible with ultra low process temperatures are needed. Nanocrystalline silicon (nc-Si:H) is a candidate, because it (a) has higher electron and hole field effect mobilities than a-Si:H, (b) is capable of CMOS operation [1], (c) is compatible with ultra-low process temperature [2], and (d) can be made by a method that is fully compatible with industrial a-Si:H technology. Plastic substrates are restricted to low tolerable process temperatures, but also have higher coefficients of thermal expansion, lower elastic moduli, and lower dimensional stability than conventional glass substrates. These characteristics pose challenges during the fabrication of electronics on plastic. A particularly serious challenge for large area fabrication is poor overlay registration [3], which could be overcome by self-aligning the appropriate layers of the thin-film circuit. Self-aligning the source and drain to the gate also would minimize the feedthrough capacitance, and would facilitate the fabrication of the short-channel TFTs that will be needed for high-speed circuits. Self-aligned amorphous-silicon TFTs with bottom gate geometry have been previously reported [4-7]. Here we demonstrate that self-alignment is possible also in the fabrication of nanocrystalline TFTs with top-gate geometry, and can be combined with lift-off patterning of the top metal contacts. This approach is particularly interesting because it is ful
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