A single-ended low leakage and low voltage 10T SRAM cell with high yield
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A single-ended low leakage and low voltage 10T SRAM cell with high yield Nima Eslami1 • Behzad Ebrahimi1
•
Erfan Shakouri1 • Deniz Najafi1
Received: 11 April 2020 / Revised: 11 April 2020 / Accepted: 30 May 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.89 higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6r in all operations, and supply voltages down to 200 mV. Keywords 10T SRAM cell FinFET Stability Low leakage power Yield Process variation
1 Introduction Nowadays, as the demand for ultra-low leakage power applications such as implantable devices in the human body, wireless sensor networks, and other portable devices has increased, the need for managing power consumption in digital chips has become an important issue [1]. SRAM cells are one of the most important components of digital chips, which consume a large percentage of power [2]. Therefore, reducing the leakage power of these memories can significantly lower the leakage power consumption of an entire chip. One way to reduce the power consumption in a cell involves reducing the operating voltage of the cell near and under the threshold voltage. However, as the supply voltage of the cell decreases below the threshold voltage, the effects of variations in the manufacturing process increase, followed by short-channel effects in technologies below 100 nm [3]. Therefore, maintaining the stability of SRAM cells poses a significant challenge in the sub-threshold region [4]. As a result, new technologies & Behzad Ebrahimi [email protected] 1
Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
have been introduced to reduce the variations in the manufacturing process and diminish the short-channel effects of nanometer technologies. One of the promising candidates is the FinFET structure because of its better gate control over the channel [5]. Despite the benefits of this technology for memory cell design, conventional 6T cell (Fig. 1(a)) still not have a proper yield in the read and write operations at low supply voltages. This is because of conflicts in the read and write requirements of conventional 6T cells, leading to a trade-off in the sizing of the cells [6]. The width qu
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