WID Rnit Variation Improvements for HSS STI CMP Process using Modified Scribe Lane Pattern Design
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WID Rnit Variation Improvements for HSS STI CMP Process using Modified Scribe Lane Pattern Design Hyuk Kwon, Yong-Soo Choi, Sang-Hwa Lee, Geun-Min Choi, Yong-Wook Song and Gyu-Han Yoon Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
ABSTRACT In the scribe lane, which is located at the frame neighboring two chips, most of the test patterns for monitoring electrical characteristics of memory device as well as various key patterns for photo process are formed. The pattern density of these regions is lower than that of the main chip area, and cause nitride erosion by dishing phenomena during HSS STI CMP process. Nitride erosion occurred in the scribe lane region, could the affect erosion properties of cell region in main chip area, results in within die remain nitride variation and marginal fail in device operation. In this work, in order to prevent these problems, pattern design in the scribe lane was modified so as not to occurs within die remain nitride variation. The effects of improvement in within die remain nitride variation were investigated by FIB-TEM analysis and its correlation with electrical properties were explained.
INTRODUCTION Recently, Ceria-based high selectivity slurry (HSS) has been used at the shallow trench isolation (STI) CMP process [1-5]. This is due to HSS has proven to give much improved field oxide (Fox) dishing and remain thickness range characteristics, as well as nitride erosion characteristics, compared to traditional silica based slurry. In the DRAM process, trench isolation technology normally requires two polishing characteristics of high polishing rate for field oxide layer and low polishing rate for nitride barrier layer. Therefore, high selectivity characteristics between oxide and nitride layer play an important role in STI CMP process and usually can be achieved using Ceria-based abrasive with additives. In the scribe lane, which is located at the frame neighboring two chips, most of the test patterns for monitoring electrical characteristics of memory device as well as various key patterns for photo process are formed. In this area, any regions that aren’t drawn at ISO mask level were generally leaved as field oxide (Fox) region. For this reason, the pattern density of these regions is generally lower than that of the main chip area, and cause nitride erosion by dishing phenomena during HSS STI CMP process. Nitride erosion occurred in the scribe lane region, could affect erosion properties of cell region in main chip area, results in within die remain nitride variation and marginal fail in device operation. In this paper, in order to prevent this problem, unit-pattern density in the scribe lane was increased by modifying some of the large Fox patterns into Active patterns. Using this modified pattern design, any possible side effects on photo key alignment process were checked. The effects of improvement in within die remain nitride variation were investigated by FIB-TEM analysis and its correlation with electrical pr
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