Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes
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CHARACTERIZING STI CMP PROCESSES WITH AN STI TEST MASK HAVING REALISTIC GEOMETRIC SHAPES Xiaolin Xie, Tae Park, and Duane Boning Microsystems Technology Laboratories, MIT, Cambridge, MA Aaron Smith, Paul Allard, and Neil Patel, National Semiconductor, South Portland, ME ABSTRACT Chemical mechanical polishing (CMP) has become the enabling planarization method for shallow trench isolation (STI) of sub 0.25µm technology. CMP is able to reduce topography over longer lateral distances than earlier techniques; however, CMP still suffers from pattern dependencies that result in large variation in the post-polish profile across a chip. In the STI process, insufficient polish will leave residue nitride and cause device failure, while excess dishing and erosion degrade device performance. Our group has proposed several chip-scale CMP pattern density models [1], and a methodology using designed dielectric CMP test mask to characterize CMP processes [2]. The methodology has proven helpful in understanding STI CMP; however, it has several limitations as the existing test mask primarily consists of arrays of lines and spaces of large feature size varying from 10 to 100 µm. In this paper, we present a new STI characterization mask, which consists of various rectangular, L-shape, and X-shape structures of feature sizes down to submicron. The mask is designed to study advanced STI CMP processes better, as it is more representative of real STI structures. The small feature size amplifies the effects of edge acceleration and oxide deposition bias, and thus enables us to study their impact better. Experimental data from an STI CMP process is shown to verify the methodology, and these secondary effects are explored. The new mask and data guide ongoing development of improved pattern dependent STI CMP models. INTRODUCTION In chemical mechanical polishing (CMP), excellent planarization (i.e., reduction in step height) of individual patterned features is achieved; however, global nonplanarity is unfortunately created mainly due to differences in the underlying pattern, resulting in nonuniform oxide thickness across the die. The ability to predict the post-CMP oxide/nitride thickness for arbitrary chip layouts is critical for STI CMP process optimization, layout screening or density design rule checking, pattern density equalization (e.g., dummy fill), and process control. Our group has previously proposed a CMP methodology involving test wafer measurement, STI CMP model calibration, and random product layout prediction [2]. The key underlying vehicle that enables characterization and modeling of STI CMP process is a test mask. The test mask can be used for rapid characterization of CMP characteristics such as consumable/tool comparisons. Furthermore, these test masks can serve as a means for developing and validating physical or semi-empirical models. The current MIT “Comprehensive Dielectric Characterization Test Mask” has proven helpful in understanding the pattern density dependence of STI CMP. However, it has several limitation
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