Characterization of Electronic Charged States of Silicon Nanocrystals as a Floating Gate in MOS Structures
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Characterization of Electronic Charged States of Silicon Nanocrystals as a Floating Gate in MOS Structures Seiichi Miyazaki, Taku Shibaguchi and Mitsuhisa Ikeda Graduate School of Advanced Sciences of Matter, Hiroshima University Kagamiyama 1-3-1, Higashi-Hiroshima 739-8530 Japan ABSTRACT We have studied capacitance-voltage (C-V) and displacement current-voltage characteristics of MOS capacitors with Si nanocrystals embedded in the gate oxide as a floating gate in dark and under visible light illumination at room temperature to gain a better understanding of discrete charged states of the Si-dots floating gate. The Si-dots floating gate with a dot density of 2.8x1011cm-2 and an average dot size of 8nm was fabricated on ~2.8nm-thick thermally-grown SiO2 as a tunnel oxide by the thermal decomposition of SiH4, and covered with 7.5nm-thick control oxide prepared by thermal oxidation of a-Si. C-V characteristics of Al-gate MOS capacitors on p-type and n-type Si(100) show unique hystereses due to the charging and discharging of the Si-dots floating gate with a symmetric pattern reflecting the Fermi level of the substrate, which enable us to rule out the contribution of traps with a specific energy state to the observed hystereses. For each of high-frequency C-V curves measured in dark, a single capacitance peak appears only around a flat-band voltage condition, which is attributed to the quick flat-band voltage shift caused by the collective emission of charges retaining in the Si-dots floating gate as confirmed from the corresponding displacement current peak. Under visible light illumination, another capacitance peak due to collective charge injection to the electrically neutral Si-dots floating gate becomes observable in the inversion condition governing the on-state of MOS FETs. Thus, the optimum bias conditions for dot-floating gate MOSFETs can be predicted from the capacitor characteristics measured under light illumination.
INTORDUCTION Si nanocrystals embedded in the gate oxide of MOS devices as charge storage nodes are attracting much attention not only from the viewpoints of their superior retention and endurance characteristics to conventional floating gate structures but also from their feasible advantage for multivalued memory operations [1-4]. To achieve clear multivalued operations at room temperature and above, discrete electronic charged states in Si-dots floating gate with an areal dot denstity larger than ~1011cm-1 have to be realized and controlled as precise as possible. In our previous work [5], we reported that, the charged and discharged states in each of nanometer Si dots can be evaluated from the surface potential change detected by an AMF/Kelvin probe technique at room temperature [5]. We have also designed and fabricated n-MOSFETs with the doubly-stacked Si-dots floating gate, and demonstrated from drain current-gate voltage (Id-Vg) characteristics and the temporal change in the drain current (Id-t) at fixed gate voltages that
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multistep electron charging to the Si-dots floati
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