Gate Technology Issues for Silicon Mos Nanotransistors
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Laboratories,Lucent Technologies, Holmdel, N.J. 07733, Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974, University of Illinois, Champaign-Urbana,Illinois 61820
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ABSTRACT This article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (- 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm INTRODUCTION Continued advancement of planar high performance sub-60 nm transistors requires ultra-thin gate dielectrics (
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