Investigations of Silicon Nano-crystal Floating Gate Memories

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Investigations of Silicon Nano-crystal Floating Gate Memories 2

Arvind Kumar, Jeffrey J. Welser, Sandip Tiwari1, Farhan Rana , and Kevin K. Chan IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A. 1 School of Electrical Engineering, Cornell University, Ithaca, NY 14853 2 Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA 02139 ABSTRACT As memory continues to be scaled to ever smaller dimensions, the floating-gate memory transistor, which offers a single-element storage cell, becomes more attractive. Typically, this structure has been reserved for nonvolatile applications, where the comparatively high voltages, slow write speeds, and limited cyclability could be tolerated. However, if the floating-gate, which is usually a continuous film of polysilicon, is replaced with a discontinuous film of small floating islands (nano-crystals), a new set of tradeoffs in these performance factors becomes possible, opening the door to broader applications. If these islands are further reduced to the point where Coulomb charging or energy quantization effects become relevant, it is possible to control the charge on the islands at a single (or few) electron level, which offers very low power operation and may enable new functionality. This paper will discuss design and fabrication of these memories, experimental results on fabricated devices, and modeling of what could ultimately be achieved, as well as what limitations will ultimately be reached. INTRODUCTION Nano-crystal memories offer several beneficial features which arise from replacing the continuous film floating gate of a flash memory with a discontinuous film of small islands [1-4], as shown schematically in figure 1. Since a discontinuous floating gate is far less susceptible to failure due to a single defect, the injection oxide can be made thinner and the memory cell can be programmed by direct tunneling, characterized by lower voltages and higher endurance than Fowler-Nordheim tunneling or hot electron injection. Furthermore, in a nano-crystal memory with weak interdot coupling, leakage to the source/drain contacts affects only a limited number of nano-crystals, allowing a more robust retention than in flash memory. Finally, if the islands are made small enough that Coulomb charging or energy quantization effects can be used to precisely control the electron occupancy of the nano-crystals [4-7], further enhancements in density become conceivable through storage of more than one bit per memory cell.

Figure 1. Schematic of a nano-crystal floating-gate transistor. F2.4.1

Figure 2. TEM and AFM images (10.0 nm vertical scale) of Si nano-crystals embedded in a gate oxide stack.

EXPERIMENT Structure and Fabrication The nano-crystals in this case are small islands or dots of silicon (Si) which have been embedded in the gate oxide of an MOS transistor, as illustrated in the TEM cross-section in figure 2. This structure is ideally fabricated as a three-layer stack using an ultrahigh vacuum chemical vapor depositio