Characterization of Plated Cu Thin Film Microstructures
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Over time at room temperature, the grains grew to greater than 1 um in size. Studied as a function of annealing temperature, the recrystallized grains were shown to be 1.6 ± 1.0/pm in size, columnar and highly twinned. The grain growth was directly related to the time dependent decrease in sheet resistance. The initial grain structure was characterized using scanning transmission electron microscopy (STEM) from a cross-section sample prepared by a novel focused ion beam (FIB) and lift-out technique. The recrystallized grain structures were imaged using FIB secondary electron imaging. From these micrographs, the grain boundary structures were traced, and an image analysis program was used to measure the grain areas. A Gaussian fit of the log-normal distribution of grain areas was used to calculate the mean area and standard deviation. These values were converted to grain size diameters by assuming a circular grain geometry. INTRODUCTION Advanced interconnects in semiconductor devices are increasingly being fabricated with electroplated Cu wiring. The change from Al to Cu interconnects has been driven by the desire to decrease signal transmission time through the use of lower resistivity Cu wiring [1]. Physical vapor deposition (PVD) aluminum interconnect processing is a mature technology with considerable understanding of Al wiring properties, physical structure and reliability. Electroplated copper, on the other hand, is an emerging technology in the semiconductor industry and research is still required to optimally fabricate and understand plated Cu wiring in devices. A specific difference between PVD Al and plated Cu thin films is the existence of a room temperature resistance transient for plated Cu. The resistance transient is a phenomena where the as-plated Cu film has a high resistivity of -2.3 la. cm and over time at room temperature, the resistivity drops by 20-25% [2-4]. This room temperature resistance drop does not occur for typical PVD Al. Previous work has attributed the resistance transient to room temperature grain growth of the plated Cu film [2-5]. In this paper, we expand upon previous work by thoroughly characterizing the microstructure of as-plated (high resistivity) and post transient (low resistivity) Cu using FIB secondary electron imaging and STEM. The grain structure was then related to the measured film properties. EXPERIMENTAL PROCEDURE All films studied in this paper were blanket metal films on Si0 2. The film stack, from bottom-to-top, consisted of: PVD barrier film / PVD Cu seed layer / electroplated Cu film. The PVD barrier and Cu seed layers were deposited sequentially without a vacuum break. The plated 373
Mat. Res. Soc. Symp. Proc. Vol. 564 © 1999 Materials Research Society
Cu was then deposited in commercially available wafer plating tools. For most of the samples studied in this paper, the plated Cu thickness was -1 um. The microstructure of plated Cu was studied at two times after plating: 1) immediately after plating (as-plated) and 2) post resistance transient. The plated fil
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