Chemical-Mechanical Planarization of Aluminum-Based Alloys for Multilevel Metallization
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MRS BULLETIN/NOVEMBER 1995
density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill. Any metal deposition process capable of filling vias can safely be assumed as capable of filling metal line patterns etched in insulator. The metals required and the deposition methods available for the gap fill are the subjects of other articles in this issue. Sputtering remains the likely method of choice for the thin-film liner materials used as adhesion and barrier layers. The bulk conductor aluminum fill will likely converge on a choice between hot sputtering, or a variation thereof, and chemical vapor deposition (CVD). For removal of the aluminum overburden, there are two candidate processes, just as there were for the removal of tungsten via overburden: reactive ion etching (RIE) etch back and chemicalmechanical polishing (CMP). Given the maturity of aluminum etch processes for metal lines, it is conceivable that a blanket metal etch back of aluminum could be developed. The RIE etch selectivity between aluminum and the underlying silicon oxide insulator is sufficiently high to allow adequate overetch in order to ensure that the entire oxide surface is
clear of residual metal that can result in intralevel shorts or reliability failures, without undue removal of interlevel insulator. The process variable most difficult to control in this scenario is the depth to which each via (or metal line, in the case of line-level damascene) is recessed below the oxide surface. This variability can result in yield losses in subsequent processing, depending on the process-integration scheme chosen. In addition, results comparing tungsten etch back with tungsten CMP3 indicate excessive leakage current between lines using etch back. The mechanisms responsible for this phenomenon suggest a similar outcome for the case of aluminum. Finally, aluminum etch back is only viable for low copper alloys, 0.5 at.% Cu typically, due to the low volatility of copper etch by-products. This limits the range of device applications for such a metallization scheme. CMP has been shown4 to be a viable process option for silicon oxide interlevel dielectric (ILD) planarization prior to first metal and following insulator deposition over each subsequent metal level. This process is a necessary step for achieving global planarization early in the multilevel metallization process, and for maintaining it following each deposition of insulator over patterned metal lines. The use of damascene CMP for tungsten overburden removal has also been demonstrated5 to be a manufacturable process. In this case, the surface is planar prior to the formation of the via holes and the via metal deposition. The role of damascene CMP is to remove the metal overburden while maintaining that planarity. In such a process-integration scheme, the CMP operations alternate
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